Sub-imaging Techniques For 3D-Interconnects On Bonded Wafer Pairs

Kong, Lay Wai; Krueger, P. J.; Zschech, Ehrenfried; Rudack, Andrew C.; Arkalgud, Sitaram; Diebold, Alain C.

doi:10.1063/1.3527129

Cited by 15 publications

(7 citation statements)

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“…The change in extrusion height of Cu-filled TSV was not measured since there had already been several reports on the extrusion measurements of Cu-filled TSV. [49][50][51] The AFM images show that the Cu-W via extrusion heights (i.e., Z axis) increased continuously with annealing durations up to 120 minutes. To describe the effect of annealing duration on extrusion behavior of Cu-W alloy, the measured extrusion heights were plotted with annealing time.…”

Section: Annealed Samplesmentioning

confidence: 98%

Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging

Roh

Sharma

Lee

et al. 2015

Metall Mater Trans A

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Extrusion behavior of Cu filling in through-silicon-via (TSV) under thermal loading was investigated in this study. In order to suppress the extrusion of Cu-filled TSV, Cu-W was filled in a tapered TSV by electroplating. The Cu-filled TSV was used as a reference for comparison. Defect less filling of Cu-W in TSV was achieved at a composition 92.4 wt pct Cu and 7.6 wt pct W. The coefficients of thermal expansion of both Cu-7.6 pctW and Cu were 10.8 9 10 À6 /°C and 16.5 9 10 À6 /°C, respectively. Initially, both Cu and Cu-W filled TSVs were annealed for 30 minutes at 723 K (450°C) and the extrusion heights were measured. The results showed that the extrusion of Cu-W filled was suppressed significantly compared to Cu-filled TSVs. The annealed extrusion heights of Cu and Cu-W were found to be 1.369 and 0.465 lm, respectively. This showed around 34 pct lower extrusion height of Cu-W filled TSV as compared to Cu-filled TSV. The extrusion kinetics with different annealing durations and the mechanism of the suppression of extrusion in Cu-W filled TSV are also reported here.

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Section: Annealed Samplesmentioning

confidence: 98%

Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging

Roh

Sharma

Lee

et al. 2015

Metall Mater Trans A

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“…Xe plasma beam columns [17,18] or laser ablation [19]. 3D nano-X-ray tomography [7] is also an attractive alternative for void inspection as it allows larger volumes to be analyzed without physical crosssectioning of the TSVs. It requires small samples and backside thinning and is hence not directly applicable to stacked devices.…”

Section: Discussionmentioning

confidence: 99%

“…Metrology challenges relate to the characterization of the Cu filling in the deep interconnects, the bonding quality between the dies, and the overlay between the dies or wafers. Scanning acoustic microscopy and confocal infrared microscopy allow imaging the interfaces through the top die or wafer [7]. The latter technique is useful for control of the overlay whereas the resolution of scanning acoustic microscopy is insufficient for that purpose.…”

Section: Introductionmentioning

confidence: 99%

“…The latter technique is useful for control of the overlay whereas the resolution of scanning acoustic microscopy is insufficient for that purpose. For the detection of voids in the interconnects, optical or SEM inspection on polished cross-sections, combined FIB/SEM analysis [8][9][10][11][12][13] or high-resolution X-ray microscopy can be used [7].…”

Section: Introductionmentioning

confidence: 99%

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FIB∕SEM Structural Analysis Of Through-Silicon-Vias

Bender¹,

Drijbooms²,

Radisic³

2011

AIP Conference Proceedings

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“…For silicon, the Raman penetration depth ranges up to 2 μm, again depending on the laser wavelength. Moreover, the Raman technique can be used to measure the near-surface stresses in Si around TSVs even with an oxide layer covering the wafer surface because the laser can penetrate the oxide layer with nearly 95% transparency [4][5][6][7][8][9][10][11][12][13][14][15]. In this paper, we reports our recent progress on the stress measurement by high efficiency micro-Raman microscopy.…”

Section: Introductionmentioning

confidence: 98%

Investigation of silicon stress around through silicon vias by high efficiency micro-Raman microscopy

Jing

Dai

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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Through silicon vias (TSVs) attract considerable amount of attention and activity in recent years as a main means to achieve three-dimensional (3D) integrated circuit (IC) functionality. However, the new technology poses new integration challenges as well as new reliability challenges. This paper presents the latest progress in TSV non-destructive stress testing by means of micro-Raman microscopy, a technique which is approved to be the method of choice for identifying stress on silicon surface. The principle of micro-Raman microscopy for TSV measurement is illustrated. By using commercially available micro-Raman microscopy tools, silicon stress around vias having a diameter of 30 μm and a depth of 160 μm has been visualized under optimized conditions.

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Sub-imaging Techniques For 3D-Interconnects On Bonded Wafer Pairs

Cited by 15 publications

References 0 publications

Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging

Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging

FIB∕SEM Structural Analysis Of Through-Silicon-Vias

Investigation of silicon stress around through silicon vias by high efficiency micro-Raman microscopy

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