Sub-Nanosecond Pulses Enable Partial Reset for Analog Phase Change Memory

Stern, Keren; Wainstein, Nicolás; Keller, Yair; Neumann, Christopher M.; Pop, Eric; Kvatinsky, Shahar; Yalon, Eilam

doi:10.1109/led.2021.3094765

Cited by 11 publications

(8 citation statements)

References 27 publications

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“…Figure b shows that the drift coefficient has an appreciable temperature-dependence, increasing as T amb increases, whereas the voltage-dependence is much less pronounced. This result is consistent with other reports in the literature. , Furthermore, higher initial resistance results in a higher drift coefficient. ,, This helps explain some anomalies in Figure b for which the drift coefficient is not higher at higher temperatures. For example, the drift coefficient at 80 K appears to be higher than the coefficient at 110 K for positive bias.…”

Section: Resultssupporting

confidence: 93%

Drift of Schottky Barrier Height in Phase Change Materials

Nir-Harwood,

Cohen,

Majumdar

et al. 2024

ACS Nano

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Phase-change memory (PCM) devices have great potential as multilevel memory cells and artificial synapses for neuromorphic computing hardware. However, their practical use is hampered by resistance drift, a phenomenon commonly attributed to structural relaxation or electronic mechanisms primarily in the context of bulk effects. In this study, we reevaluate the electrical manifestation of resistance drift in sub-100 nm Ge2Sb2Te5 (GST) PCM devices, focusing on the contributions of bulk vs interface effects. We employ a combination of measurement techniques to elucidate the current transport mechanism and the electrical manifestation of resistance drift. Our steady-state temperature-dependent measurements reveal that resistance in these devices is predominantly influenced by their electrical contacts, with conduction occurring through thermionic emission (Schottky) at the contacts. Additionally, temporal current–voltage characterization allows us to link the resistance drift to a time-dependent increase in the Schottky barrier height. These findings provide valuable insights, pinpointing the primary contributor to resistance drift in PCM devices: the Schottky barrier height for hole injection at the interface. This underscores the significance of contacts (interface) in the electrical manifestation of drift in PCM devices.

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Section: Resultssupporting

confidence: 93%

Drift of Schottky Barrier Height in Phase Change Materials

Nir-Harwood,

Cohen,

Majumdar

et al. 2024

ACS Nano

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Section: Synaptic Devices For Neuromorphic Computingmentioning

confidence: 99%

“…proposed a method to precisely control the melt volume by applying electric pulses shorter than the thermal time constant (τ th ) that is the time required for the critical volume of a phase‐change material to reach its melting point. [ 79 ] By applying identical 0.4 ns pulses to the confined‐type PCM, they achieved an on/off ratio of ≈20×, 50 states of gradual LTD within a partial reset regime (Figure 4d). Linearity can also be improved by limiting the phase‐change volume.…”

Section: Synaptic Devices For Neuromorphic Computingmentioning

confidence: 99%

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Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Byun

Choi

Kwon

et al. 2022

Adv Materials Technologies

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Nonvolatile memory (NVM)‐based neuromorphic computing has been attracting considerable attention from academia and the industry. Although it is not completely successful yet, remarkable achievements have been reported pertaining to synaptic devices that can leverage NVM capable of storing multiple states. The analog synaptic devices performing computation similar to biological nerve systems are crucial in energy‐efficient analog neuromorphic computing systems. To use NVM as an analog synaptic device, researchers focus on improving device characteristics. Among various characteristics, the most challenging one is linearity and symmetry of synaptic weight update that is required for on‐chip training. In this regard, this review paper discusses recent synaptic device improvements focusing on novel schemes tailored for each NVM device to improve the linearity and symmetry. In addition to device‐level studies, recent research achievements are reviewed expanded up to chip‐level studies because in realizing neuromorphic hardware systems beyond a single synaptic device, several considerations and requirements are needed to confirm for high‐level design, and accordingly, cooptimize among synaptic devices, synapse arrays, electrical circuits, neural networks, algorithms, and implementation. Also, this review paper introduces various circuit and algorithmic approaches to compensate for the non‐ideality of the analog synaptic device.

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“…[33,36] According to this theory, the decrease in the final resistance after the subsequent bias pulse upon a stimulus can be described by its history of cluster-size redistribution. In the cases of the primed state [40] or partially crystallized states, [41] they can be described by their enhanced degree of medium-range order or crystallization, respectively, compared to the disordered network structure of the amorphous state that fluctuates locally after excitations. From the point of view of the kinetic theory of nucleation, this corresponds to the case that, in response to a temperature change, the cluster population of the melt-quenched amorphous state n am (the blue lines in Figure 2c,d) evolves gradually to the steady-state cluster-size distribution for the primed state n p (t) (the green line in Figure 2c), to the one for partially crystallized states n pc,i (t), n pc,ii (t), and n pc,iii (t) (the green lines in Figure 2c,d), and finally to n c,ss (for the fully crystallized state) at an increased temperature.…”

Section: Resultsmentioning

confidence: 99%

Toward Single‐Cell Multiple‐Strategy Processing Shift Register Powered by Phase‐Change Memory Materials

Wang

Huang

et al. 2023

Advanced Intelligent Systems

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Computers are the foundations of everything from weapons systems to technologies utilized daily by businesses and consumers. The ever-increasing demand for data-intensive applications in business-related fields including machine learning and the internet of things requires highly energy-efficient hardware for operations such as autonomous driving, [1,2] speech recognition, [3,4] image classification, [5] and diseases diagnosis. [6] Moreover, there is an ever-rising demand for readily-accessible-data utilizations in consumer-grade products such as televisions, laptops, and tablets that require advanced technologies, e.g., during the Covid-19 pandemic, as people worked and learned via Zoom, socialized over Skype, and engaged on Netflix to alleviate the lockdown blues. Because these data-intensive/ readily-accessible-data applications require both high performance and energy-efficient operation, the power [7,8] and memory constraints imposed by von Neumann computers, with separate processing and storage units, limit the ability of conventional processors to meet optimal requirement for these applications. [9] Traditional computers utilize a wide range of memory technologies. [10,11] Prototypical register/static random-access memory (SRAM) technologies are fast (few nanoseconds) but volatile and have a low integration density, which limits their use to high-speed/ cache memory applications. [12] The register, based on a set of flip flops, plays a key role in accepting, storing, and transferring data and instructions that are being utilized immediately by the CPU, as well as other digital circuitries. [13] The data can be transferred in a serial manner using shift-based operations. [14] Moreover, conventional dynamic random-access memory (DRAM) technology is moderately fast (several ten nanoseconds) but volatile. [15] As a result, prototypical DRAM requires frequent refresh operations and thus has increased energy consumption. On the other hand, typical flash is nonvolatile but relatively slow (hundreds of microseconds). [11,16]

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Sub-Nanosecond Pulses Enable Partial Reset for Analog Phase Change Memory

Cited by 11 publications

References 27 publications

Drift of Schottky Barrier Height in Phase Change Materials

Drift of Schottky Barrier Height in Phase Change Materials

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Toward Single‐Cell Multiple‐Strategy Processing Shift Register Powered by Phase‐Change Memory Materials

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