SUBHDIP: process variations tolerant subthreshold Darlington pair‐based NBTI sensor circuit

Shah, Ambika Prasad; Yadav, Nandakishor; Beohar, Ankur; Vishvakarma, Santosh Kumar

doi:10.1049/iet-cdt.2018.5123

Cited by 6 publications

(5 citation statements)

References 26 publications

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“…The V out is a function of the output resistance and trans-conductance of the transistors. The sensitivity of the proposed sensor defined by the ratio of the change in output to the change in input as s = ∆V out /∆I in , has the value of 0.4 mV/nA which is much higher than the sensitivity of the SUBHDIP sensor [20]. The input resistance in the proposed circuit is very high due to the presence of the gate oxide and a diode-connected transistor.…”

Section: Out I Ddqmentioning

confidence: 94%

“…In order to demonstrate the effect of process variation on the proposed sensor, 5000 Monte Carlo simulations were performed to show the variation in the threshold voltage. The Simulation result is shown in Figure 10 which shows that the mean value µ and the standard deviation (SD) σ of the output voltage are smaller than those of the outputs generated by the state-of-the-art designs [20]. Input Current(A)…”

Section: Proposed Stress Measurement Sensormentioning

confidence: 97%

“…Simulation result of the sensor shown in Figure 9 shows the ability of the proposed sensor circuit to achieve a large change in the output voltage with a small change of the input current. The range of the output voltage swing ranges from 0.1 V to 0.75 V at 1 V supply, which is higher than the output voltage ranges achieved by the state-of-the-art sensor [20]. In order to demonstrate the effect of process variation on the proposed sensor, 5000 Monte Carlo simulations were performed to show the variation in the threshold voltage.…”

Section: Proposed Stress Measurement Sensormentioning

confidence: 99%

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A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

Yadav¹,

Kim²,

Alashi³

et al. 2020

Electronics

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Process Variation (PV), Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB) are the critical factors that affect the reliability of semiconductor chip design. They cause the system to be unstable and increase the soft error rate. In this paper, a compact on-chip degradation technique using runtime leakage current monitoring has been proposed. The proposed sensor-based adaptive technique compensates for the variation due to PV and aging using the body-bias-voltage-generator circuit. Simulation experiments for three and ten-year stress have been performed. Simulation results proved the superiority of the proposed sensor which provides 33% (up to 0.75 V) more output voltage and 98% sensitivity at 1 V supply voltage compared to the state-of-the-art sensor. The proposed technique mitigates up to 80% PV and BTI effects in SRAM compared to the state-of-the-art techniques.

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Section: Out I Ddqmentioning

confidence: 94%

Section: Proposed Stress Measurement Sensormentioning

confidence: 97%

Section: Proposed Stress Measurement Sensormentioning

confidence: 99%

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A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

Yadav¹,

Kim²,

Alashi³

et al. 2020

Electronics

Self Cite

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“…Meanwhile, the aging sensors that were proposed by A. Amouri et al [27] place the aging sensor in a critical path to avoid late transitions occurring in the circuit. The aging sensor [28,29] and FPGA chips were reprogrammed to reduce the late transition effects caused by NBTI [30] and hot carrier injection (HCI). Meanwhile, M. Valdes-Pena proposed an aging sensor without determining a specific delay range [31].…”

Section: Lifetime Reliability Sensing In Fpgasmentioning

confidence: 99%

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

et al. 2021

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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“…Tabular analysis (Table 1) of the results obtained by [9] reveals that:(a) the shift in threshold voltage (V th ) and drain current (I dd ) is a function of high temperature and is observed to increase for V th and decrease for I dd at temperatures ≥ 60 • C, (b) an approximate rise of 4% in the threshold voltage shift is evident with the scaling down of technology nodes [44]. The rate of decrease in I dd is, however, less than the rate of V th increase, and (c) eventually, the propagation delays increase with the aforementioned trends of variation in V th and I dd .…”

Section: A Design Considerationsmentioning

confidence: 99%

Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

et al. 2020

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The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship's integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillatorbased sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation. INDEX TERMS Ageing mechanism, field programmable gate array (FPGA), hardware Trojan, negative bias temperature instability (NBTI), propagation delay, reliability, threshold voltage. I. INTRODUCTION A modern FPGA is not merely an emulator but a hardware accelerator with heterogenous hard IP cores, such as complex memory blocks, multiple processors, and DSP blocks. Systems on chip (SoC), network on chip (NoC), and adaptive compute acceleration platform (ACAP) are the significant performance and functional enhancements of FPGAs, that have been made possible due to the continual shrinking of transistor sizes down to the scales of 10 nm and below. The performance benefits, however, are limited by power The associate editor coordinating the review of this manuscript and approving it for publication was Luis Javier Garcia Villalba. and timing closures. Similarly, the geometric structures of FPGAs with much less silicon and relatively more oxide and moulding compound complicate the heat conduction paths [1]. On the one hand, where it may deteriorate the worstcase heat dissi...

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SUBHDIP: process variations tolerant subthreshold Darlington pair‐based NBTI sensor circuit

Cited by 6 publications

References 26 publications

A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

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