Submicron-Scale Cu RDL Pattering Based on Semi-Additive Process for Heterogeneous Integration

Takano, Takamasa; Kawamura, Hiroshi; Tanaka, Masaya; Akazawa, Miyuki

doi:10.1109/ectc.2019.00022

Cited by 10 publications

(2 citation statements)

References 11 publications

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“…A competitive alternative to SAP [4] and LELE [5] for N+3 node is a combination of material, process and tool development: a grey-tone dual damascene optimization of PIDs with a maskless computation architecture for submicron printing called Digital Lithography Technology or DLT. This lithography technology (Figure 4) is particularly suitable for packaging as it is scalable with highest resolution at production throughput and overlay performance, and modular with patterning capabilities on all substrate materials and sizes.…”

Section: Discussionmentioning

confidence: 99%

Performance comparison of photosensitive polyimides for high-resolution dual-damascene schemes for FOWLP packaging applications

Bozano,

Quon,

Briggs

et al. 2024

Advances in Patterning Materials and Processes XLI

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Advanced AI systems require more exotic packaging solutions to increase performance and manage power loads. Packaging designers not only need increased interconnect density through pitch scaling, but also seek to print this advantage over areas beyond the capability of standard lithography. These demands call for innovations in materials, processes, integrations, and tools for packaging.In a bid to find solutions for finer L/S pattern in redistribution layers, photo-imageable polyimides (PIDs) from different vendors were tested for performance properties (resolution, dose to size, sidewall quality) using direct write exposure methods, and then assessed for compatibility in a dual damascene (DD) integration for FOWLP packaging.

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Section: Discussionmentioning

confidence: 99%

Performance comparison of photosensitive polyimides for high-resolution dual-damascene schemes for FOWLP packaging applications

Bozano,

Quon,

Briggs

et al. 2024

Advances in Patterning Materials and Processes XLI

View full text Add to dashboard Cite

show abstract

“…These techniques narrow the RDL trace width/pitch to as small as two microns [ 11 , 12 ] and even sub-microns [ 13 ]. To enhance the electricity transmission capacity, traces become thicker, with an aspect ratio of up to 4.2 [ 14 ], which is very different from traditional shell-like thin traces. Furthermore, wafer-level integrations can stack up to five metal layers [ 1 ], with an area up to 1200 mm 2 [ 15 ] or even as extensive as 2500 mm 2 [ 1 ].…”

Section: Introductionmentioning

confidence: 99%

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Wu,

Wang,

et al. 2023

Micromachines

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The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.

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Advances in Photosensitive Polymer Based Damascene RDL Processes: Toward Submicrometer Pitches With More Metal Layers

Chery

Slabbekoorn

Pinho

et al. 2021

2021 IEEE 71st Electronic Components and Technology Conference (ECTC)

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Submicron-Scale Cu RDL Pattering Based on Semi-Additive Process for Heterogeneous Integration

Cited by 10 publications

References 11 publications

Performance comparison of photosensitive polyimides for high-resolution dual-damascene schemes for FOWLP packaging applications

Performance comparison of photosensitive polyimides for high-resolution dual-damascene schemes for FOWLP packaging applications

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Advances in Photosensitive Polymer Based Damascene RDL Processes: Toward Submicrometer Pitches With More Metal Layers

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