Substrate-aware mixed-signal macrocell placement in WRIGHT

Abstract

Absfract-We describe a set of placement algorithms for handling substrate-coupled switching noise. A typical mixedsignal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digitavanalog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these suhstrateaware algorithms allow efficient mixed-signal placement optimization.

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

“…Although automated placement tools can be used for minimizing substrate noise [26], [30], it is useful for a designer to understand the impact of certain placement/layout decisions. To illustrate this, we evaluate the influence of various factors on substrate noise coupling.…”

Computer-aided design of analog and mixed-signal integrated circuits

“…The WREN [130] and WRIGHT [131] tools generalized these ideas to the case of arbitrary layouts of mixed functional blocks. WREN comprises both a mixed-signal global router and channel router [130].…”

“…WREN incorporates a constraint mapper that transforms input noise rejection constraints from the across-the-whole-chip form used by the global router into the per-channel per-segment form necessary for the channel router. WRIGHT on the other hand uses simulated annealing to floorplan the blocks, but with an integrated fast substrate-noise-coupling evaluator so that a simplified view of substrate noise influences the floorplan [131]. Fig.…”

Standard cell placement for even on-chip thermal distribution

“…In [7] the effects of substrate noise coupling were included in the cost function of a simulated annealing-based power distribution synthesis system. Similarly, in [8] the impacts of substratecoupled switching noise were also considered in the simulated annealing-based macrocell placement tool WRIGHT. Although the problems are similar, our approach is quite different from these works.…”

“…Although the problems are similar, our approach is quite different from these works. In both [7] and [8], a timeconsuming procedure was needed in the inner loop of the simulated annealing process to simulate the noise effects of the current placement configuration, resulting in excessively long computation time. No such expensive computation is needed in our method.…”