2016
DOI: 10.1080/00207217.2016.1180546
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Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

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Cited by 4 publications
(6 citation statements)
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“…An EδDC transistor is a device structure proposed by us which is reported to be a low-power, low-cost transistor, suitable for SoC applications with controlled process variability effects due to random discrete dopant effects [12], [13], [14], [15], [16], [17]. In the present work, we derive a physics based local drain current variability model of an epitaxial delta doped channel MOS (EδDC) transistor, caused due to random fluctuation of channel length, attributed to the LER/LWR phenomenon.…”
Section: Outline and Contribution Of Our Workmentioning
confidence: 99%
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“…An EδDC transistor is a device structure proposed by us which is reported to be a low-power, low-cost transistor, suitable for SoC applications with controlled process variability effects due to random discrete dopant effects [12], [13], [14], [15], [16], [17]. In the present work, we derive a physics based local drain current variability model of an epitaxial delta doped channel MOS (EδDC) transistor, caused due to random fluctuation of channel length, attributed to the LER/LWR phenomenon.…”
Section: Outline and Contribution Of Our Workmentioning
confidence: 99%
“…This leads to the nature of variation of normalized drain current variability even for similar fluctuation σI D over the entire gate bias range. As evident from (16) In the weak inversion mode (WI), the local drain current variability depends upon three factors: the channel length variability, the threshold voltage variability and the correlation factor. Since the channel length variability term is bias independent, the drain bias dependence comes from the remaining two components.…”
Section: Variation Of Local Drain Current Variability With Biasmentioning
confidence: 99%
“…An EδDC transistor is a device structure proposed by us which is reported to be a low-power, low-cost transistor, suitable for SoC applications with controlled process variability effects due to random discrete dopant effects [12], [13], [14], [15], [16], [17]. In the present work, we derive a physics based local drain current variability model of an epitaxial delta doped channel MOS (EδDC) transistor, caused due to random fluctuation of channel length, attributed to the LER/LWR phenomenon.…”
Section: Outline and Contribution Of Our Workmentioning
confidence: 99%
“…The last term in (16) is the correlation coefficient. The current sensitivities are calculated using (12) and (13).…”
Section: Drain Current Variability In Weak Inversion (Wi) Modementioning
confidence: 99%
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