Substrate noise coupling through planar spiral inductor

Abstract

While previous studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radio frequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise sensor is less than 030 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tunedgain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using broken guard ring in reducing inductor induced substrate noise is also examined.

Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding

“…Pun et al [25] investigated the substrate noise pattern induced through planar inductors and a grounded guard ring was proposed as one of the remedies to mitigate the crosstalk. In fact, the usefulness of reducing the substrate coupling noise by inserting ground TSVs in between signal TSVs had been reported earlier [26].…”

“…Similarly, for configuration B, the power loss P B will be the addition of power loss in the ground TSVs (g 1 -g 6 ) to the inductor TSVs (T 1 -T 4 ). P A and P B are calculated according to [31] as in expressions (25) and (26) by considering identically layered TSV windings. Earlier, it was established that the mutual inductance change for those two configurations is less than 1%.…”

SPICE simulation and tradeoffs of CMOS LNA performance with source-degeneration inductor

“…A substrate depth of 5 µm, rather than a full wafer depth of hundreds of micrometers was simulated. However, the epi-substrate nature of the process would guarantee that the omitted depth is mostly highly doped and will not severely affect the results [5]. A frequency sweep from 1 to 26 GHz was performed on the device.…”

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

“…However, there are limitations in performance and device-parameters of integrated passive devices on a silicon (Si)-wafers [5]- [7]. Another method is making passive components in a printed circuit board (PCB), and connect them to ICs on top of the PCB [8], [9].…”