Substrate noise modeling with dedicated CAD framework for smart power ICs

Zeng, Hao; Moursy, Yasser; Iskander, Ramy; Stefanucci, Camillo; Buccella, Pietro; Kayal, Maher; Sallèse, Jean-Michel

doi:10.1109/iscas.2015.7168943

Cited by 6 publications

(7 citation statements)

References 7 publications

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“…They inherently model the minority carriers propagation in the substrate. The enhanced diodes, resistors, and homojunction models allow modeling these parasitic components [8]. AUTOMICS is a parasitic extraction tool that is capable of modeling the substrate including the minority carriers propagation.…”

Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

“…The inputs and outputs of the tool are depicted in Figure 1. The main flow of the tool can be divided into three main stages [8], [9]: preprocessing stage, extraction stage, and post-processing stage. The input is the layout of the design.…”

Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

“…AUTOMICS substrate parasitic extraction flow. [8] and parameters calibration is performed to fit the simulation results and measurements [14].…”

Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

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Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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Abstract-This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The proposed methodology employs a dedicated tool for substrate network generation referred to as AUTOMICS. We applied the methodology on two test cases. The first case is a DC-DC buck converter chip fabricated with a 0.35 µm HV-CMOS technology. The DC coupling current between the switches and the bandgap circuit is simulated and verified with measurements. The second test case is an automotive industrial chip that has a latch-up failure due to substrate coupling. In transient simulations, the failure has been reproduced as in measurements. This highlights the stronghold of the methodology since it can be used to prevent this type of failures before fabrication. The proposed methodology can reduce the number of redesigns in the automotive industry. Hence, it shortens the time-to-market, improves the robustness of the design, and reduces the cost.

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Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

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Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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“…A non-uniform meshing mechanism is used to reduce the complexity. The extraction phase, parasitic devices are extracted and classified based on the doping profiles and orientation [6]. A netlist describing the extracted parasitic components is generated.…”

Section: A Automics Tool Geometrical Features Extractionmentioning

confidence: 99%

Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs

Moursy

Zeng

Iskander

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-In this paper, a proposed methodology to identify the substrate coupling effects in smart power integrated circuits is presented. This methodology is based on a tool called AUTOMICS to extract substrate parasitic network. This network comprises diodes and resistors that are able to maintain the continuity of minority carrier concentration. The contribution of minority carriers in the substrate noise is significant in high-voltage and high temperature applications. The proposed methodology along with conventional latch-up problem identification for a test case automotive chip AUTOCHIP1 are presented. The time of the proposed methodology is significantly shorter than the conventional one. The proposed methodology could significantly shorten the time-to-market and ameliorate the robustness of the design.

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“…The IC substrate can be modeled with a parasitic network of three lumped components: the EPFL diode, the EPFL resistance and the the EPFL homojunction. This network is highly dependent on the chip layout and can be automatically extracted processing the used mask layers [13]. Across PN junctions a diode is instantiated which injects or collects minority carriers, in the bulk substrate resistances are used to propagate the charges while at PP+ NN+ doping discontinuities the homojunction model is used.…”

Section: Substrate Current Modelmentioning

confidence: 99%

Substrate modeling to improve reliability of high voltage technologies

Stefanucci¹,

Buccella²,

Moursy³

et al. 2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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In Smart Power ICs there is the need of new substrate models to be integrated in the design flow of power circuits. This work reports the latest results regarding the substrate modeling methodology based on three-dimensional lumped components extraction of diodes, resistors and contacts. The substrate network including lateral and vertical parasitic bipolar transistor can be automatically created from any chip layout including temperature and geometry variations. In such a way fast dc and transient analysis can be carried out in early design stages to improve reliability of high voltage ICs. Since the high variability and complexity on modern Smart Power technologies, a flexible model is required. This work discusses all the features related to technology variations. Circuit simulator results are then compared with TCAD simulations.

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Substrate noise modeling with dedicated CAD framework for smart power ICs

Cited by 6 publications

References 7 publications

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs

Substrate modeling to improve reliability of high voltage technologies

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