Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions

Koley, Kalyan; Syamal, Binit; Kundu, Atanu; Mohankumar, N.; Sarkar, Chandan Kumar

doi:10.1016/j.microrel.2012.06.110

Cited by 32 publications

(19 citation statements)

References 10 publications

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“…However, with decrease in channel length beyond 100 nm, the short channel effects for bulk metal-oxidesemiconductor (MOS) structure increases considerably causing higher leakage current and power loss. To handle the leakage power and short channel effect, one of the possible alternatives is to use underlap double-gate MOS (DGMOS) structure [2,3]. This devices structure also offers an enhanced control over the channel current due to introduction of the additional back gate which in turn improves the circuit performance in analogue domain [4].This device configuration has also been found to offer a very large bandwidth which is crucial for RF circuit designs.…”

Section: Introductionmentioning

confidence: 99%

Low‐power amplitude modulator for wireless application using underlap double‐gate metal–oxide–semiconductor field‐effect transistor

Mukherjee

Koley

Dutta

et al. 2016

IET Circuits, Devices & Systems

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In this study, a design guideline for a modified low-power wideband on-chip amplitude modulator (AM) based on independently driven double-gate metal-oxide-semiconductor field-effect transistor (IDDGMOS) is proposed. The AM performance is then analysed for three different types of underlap engineered IDDGMOS devices. It is observed that the modulator designed with IDDGMOS presents a higher gain and bandwidth for lower power input signals. For analysing the gain-bandwidth performance of the modulator circuit, a small signal model for the devices is considered. The linearity and noise performance of the modulator circuit for different IDDGMOS structures is analysed by studying the 1 dB compression point and the signal-to-noise ratio. The analysis suggested that the most efficient AM circuit performance is achieved for the symmetric underlap IDDGMOS device. The symmetric underlap IDDGMOS AM circuit yields a gain of 11 dB, a bandwidth of 5.5 GHz and a 47.2% efficiency with a distortion less input signal power range of −60 to −33.5 dB. Moreover, the reduced power loss is about 0.047% of the power loss obtained for the conventional complementary metal-oxide-semiconductor device, whereas the bandwidth of the circuit almost triplicates.

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Section: Introductionmentioning

confidence: 99%

Low‐power amplitude modulator for wireless application using underlap double‐gate metal–oxide–semiconductor field‐effect transistor

Mukherjee

Koley

Dutta

et al. 2016

IET Circuits, Devices & Systems

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“…Though, the Underlap-FinFETs show superior device performance, it suffers from a large distributed channel resistance (R ch ) which eventually degrades the on current (I on ). To overcome these limitations, various measures like the use of asymmetric source/drain extensions and applications of high κ spacer engineering have been reported [12]- [13]. In this paper, a gate engineering technique is used to improve the Underlap-FinFET device performance for low power analog/RF applications.…”

Section: Introductionmentioning

confidence: 99%

Influence of the Gate Height Engineering on the Intrinsic Parameters of UDG-MOSFETs With Nonquasi Static Effect

Ghosh

Koley

Saha³

et al. 2015

IEEE J. Electron Devices Soc.

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“…To minimize the SCEs, several modifications of MOSFET device have evolved. One such prominent contender is asymmetric underlap double-gate MOSFET (AUDG-MOSFET) [1]- [3]. The AUDG-MOSFET structure is specified by a drain end underlap.…”

Section: Introductionmentioning

confidence: 99%

“…The introduction of the underlap also reduces the gate-induced drain leakage and fringing capacitance. It has been established that AUDG-MOSFETs Manuscript offer a superior analog and RF performances by proper optimization of the underlap length [3]. However, AUDG-MOSFETs suffer from low ON current (I ON ) and higher distributed channel resistance compared with conventional double-gate (DG) MOSFETs (DGFETs).…”

Section: Introductionmentioning

confidence: 99%

Analysis of High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Spacer Asymmetric Underlap DG-MOSFET for SOC Application

Koley

Dutta

Saha³

et al. 2015

IEEE Trans. Electron Devices

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In this paper, asymmetric underlap doublegate (AUDG) MOSFET is studied to analyze the influence of high-k spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high-k spacers. To evaluate the device performance and to study the improvement associated with the use of high-k spacers, different intrinsic parameters are analyzed. These parameters include transconductance (g m ), transconductance generation factor (g m /I d ), intrinsic gain (g m r o ), intrinsic capacitance (C gd , C gs ), resistance (R gd , R gs ), transport delay (τ m ), inductance (L sd ), cutoff frequency ( f T ), and the maximum frequency of oscillation ( f max ), gain bandwidth product, and inverter delay. Index Terms-Asymmetric underlap double-gate (AUDG)FET, high-k, intrinsic parameter spacer.

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Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions

Cited by 32 publications

References 10 publications

Low‐power amplitude modulator for wireless application using underlap double‐gate metal–oxide–semiconductor field‐effect transistor

Low‐power amplitude modulator for wireless application using underlap double‐gate metal–oxide–semiconductor field‐effect transistor

Influence of the Gate Height Engineering on the Intrinsic Parameters of UDG-MOSFETs With Nonquasi Static Effect

Analysis of High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Spacer Asymmetric Underlap DG-MOSFET for SOC Application

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