2020
DOI: 10.1109/jeds.2020.2988730
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Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Abstract: This work was supported by Intel.

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Cited by 30 publications
(12 citation statements)
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“…1c, d [22]. Moreover, the degradation of active device matching [23] and the improvement of the quality factor of on-chip passive components [24], necessitate careful characterization and modeling for circuits operated at cryogenic temperatures.…”
mentioning
confidence: 99%
“…1c, d [22]. Moreover, the degradation of active device matching [23] and the improvement of the quality factor of on-chip passive components [24], necessitate careful characterization and modeling for circuits operated at cryogenic temperatures.…”
mentioning
confidence: 99%
“…Due to the cryogenic shift in device performance and the numerical instability in the foundry device models when extrapolated beyond their range of validity, also standard foundry models cannot be used at cryogenic temperatures. Still, by comparing characterization data [25], [26] at 300 and 4.2 K, boundaries for the main relevant changes in device and circuit behavior can be derived to ensure robust circuit design, although unfortunately no circuit simulations can be performed.…”
Section: Cryo-cmos Design Challengesmentioning
confidence: 99%
“…The sub-DACs are then sequentially enabled to create a symmetric pulse of current, which is filtered and upconverted. This approach guarantees a smooth pulse due to the inherent monotonicity of the rising and falling edges, overcoming challenges related to MOSFET mismatch degradation at cryogenic temperatures [48], [49]. The mixer center tap is grounded through a balance resistor, providing a ground return for the single-ended current pulse.…”
Section: A Xy Controllermentioning
confidence: 99%