SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs

Abstract

A methodology is presented for generating conipact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns i s efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and translated into an energy spectrum which accounts for fundamental frequencies as well as glitch energy. Preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.

Theoretical and practical validation of combined BEM/FEM substrate resistance modeling

“…To predict any problems in circuit performance caused by substrate noise, there is an increasing need for accurate models that describe the noise-propagation behaviour of the substrate [1,2,3,4,5,6,7,8,9,10]. Such models are usually obtained through either the Finite Element Method (FEM) as applied in e.g.…”

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects

“…For every gate, a substrate noise current signature is extracted for every switching activity at the inputs. In [3] [4], only switching at the outputs, which is coupled into the substrate via the drain capacitance, is taken into account, not at the inputs and the effects of the noisy power supply. We have presented a methodology named SWAN (Substrate Waveform ANalysis) [6] [7], which accurately simulates the actual waveform of the substrate noise voltage of a large digital circuit by considering both power supply coupling (Ldi/dt) and capacitive coupling (CdV/dt).…”

“…For substrate noise the first effort to model gates with a lumped equivalent model has been made in [2] where a digital gate is modeled by a current source in parallel with its circuit and n-well capacitance. Methodologies that make use of real substrate noise waveforms extracted for each standard cell are presented in [3][4] [5]. For every gate, a substrate noise current signature is extracted for every switching activity at the inputs.…”

A macromodelling methodology for efficient high-level simulation of substrate noise generation

“…A review of the most important existing methodologies for the substrate noise analysis and simulation is performed (SubWave methodology, from Berkelay [1], University of Hiroshima macromodelling approach [2] and SWAN methodology from IMEC [3]). The modelling of the substrate, that can be considered a resistive mesh between the substrate nodes of interest for frequencies up to a few GHz [4] is addressed using commercial CAD tools like SubstrateStorm from Cadence [5].…”