A macromodelling methodology for efficient high-level simulation of substrate noise generation

Abstract

Efficient prediction of the substrate noise generated by digital sections is currently a major challenge in System-ona-Chip design. In this paper a macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel accuracy is demonstrated for some simple circuits.

Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL

“…There has been much work on efficiently modeling noise generation in digital circuits using noise macromodels [1] [2]; however, because these approaches require a circuit layout, they are limited to use as a final verification tool. Early in the design cycle, a layout may not be available; thus, a substrate noise estimate cannot be determined.…”