Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

Abstract

The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices*

“…In our previous work, we reported that the surface-nitrided Si-NC NVM devices show low subthreshold swing, which is due to good passivation of the Si-NC surface defect during the nitridation treatment. [17] After the erasing operation under a −7-V pulse voltage of 1 ms, the transfer characteristic curves of five kinds of test key cells are in good agreement with each other. After the programming operation under +7 V pulse voltage of 1 ms, the transfer characteristic curves are also in good agreement with each other.…”

“…The details of sample fabrication can be found in our previous work. [17] As listed in Table 1, eight kinds of test key cells with different gate widths and lengths are defined. The topographic-view AFM, SEM images, and statistic size distribution for Si-NCs are shown in Fig.…”

“…In our previous work, we reported that the electrical performance of test key cell D, which shows the characteristics of superior endurance, faster P/E speed, and good data retention. [17] Here, we take test key cell D as a reference cell. The x axis represents the area difference between the gate and the reference cell (∆S).…”

Temperature-Dependent Growth of Crystalline Silicon Quantum Dots Embedded in Silicon Nitride

“…Since 1990 [1], silicon quantum dots (Si QDs) have been intensively studied because of the possibility of applications such as compatible metal-oxide-semiconductor (CMOS) devices [2], light source [3][4][5], fluorescent tags for biomedical applications [6], and their novel applications with electrical and optical functions. For accomplishment of various applications, we need to be trying to understand how to control the size of Si QD embedded in an insulating layer.…”

SiGeSn Quantum Dots in HfO2 for Floating Gate Memory Capacitors

“…Group IV quantum dots (QDs) are attractive for non-volatile memories (NVMs) considering their compatibility with CMOS technology [1][2][3][4][5][6][7][8][9][10]. Additionally, QDs can tune NVM device parameters related to performance and stability by tailoring their size, density, and interface quality with embedding oxide [11][12][13][14].…”