Supervisory Circuits for Low-Frequency Monitoring of a Communication SoC

Furth, Paul M.; Veerabathini, Anurag; Saifullah, Z. M.; Rivera, Derrick T.; Elkanishy, Abdelrahman; Badawy, Abdel-Hameed A.; Michael, Christopher P.

doi:10.1109/mwscas.2019.8885315

Cited by 7 publications

(2 citation statements)

References 6 publications

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“…Switching converters have output voltage ripples that make them not suitable for all applications. Low drop-out (LDO) regulators are popular when a clean and quiet power supply is required [5]. The LDO regulators are efficient when the output voltage is close to the input supply voltage, and its efficiency is the ratio of output to input voltage.…”

Section: Introductionmentioning

confidence: 99%

Improved Frequency Compensation Technique for Three-Stage Amplifiers

Roman‐Loera

Veerabathini

Oropeza

et al. 2021

JLPEA

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Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.

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Section: Introductionmentioning

confidence: 99%

Improved Frequency Compensation Technique for Three-Stage Amplifiers

Roman‐Loera

Veerabathini

Oropeza

et al. 2021

JLPEA

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“…Switched-capacitor (SC) DC-DC converters have the advantage of monolithic integration of the converter with no off-chip inductors. SC converters achieve efficiency greater than an LDOwhen the output voltage is not close to the input voltage [5]. The peak theoretical efficiency of a step-down SC converter can be described using the relation [6]: η PK ≈ P OUT P OUT + P BP + P SW + P DR + P LK + P CTRL (1) where P OUT is the output power, P BP is power loss from the parasitic bottom-plate (BP) capacitance of the charge transfer capacitor, P DR is the gate driver loss, P SW is the switch loss, P LK is the power loss due to subthreshold leakage current through the power switches in the off-state, and P CTRL is the power loss in the controller.…”

Section: Introductionmentioning

confidence: 99%

High-Efficiency Switched-Capacitor DC-DC Converter with Three Decades of Load Current Range Using Adaptively-Biased PFM

Veerabathini

Furth

2020

JLPEA

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A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the range of 12 μ A to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to <72 mV over the entire load current range.

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