Suppression of corner effects in triple-gate MOSFETs

Fossum, J.G.; Yang, Ji-Woon; Trivedi, Vishal

doi:10.1109/led.2003.820624

Cited by 119 publications

(62 citation statements)

References 6 publications

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“…Here we focus on short devices with 60 nm gate length where the subthreshold regime exhibits specific conductance peaks due to isolated dopants in the channel. All the measurements presented here were gathered on the same sample, but similar features have been observed in other samples of the same length (the width, 385 nm here, is not important because of a corner-effect [11,12] ). The experiments were carried out in a dilution fridge at a base temperature of 100 mK.…”

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confidence: 76%

Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire

et al. 2006

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We report on spectroscopy of a single dopant atom in silicon by resonant tunneling between source and drain of a gated nanowire etched from silicon on insulator. The electronic states of this dopant isolated in the channel appear as resonances in the low temperature conductance at energies below the conduction band edge. We observe the two possible charge states successively occupied by spin-up and spin-down electrons under magnetic field. The first resonance is consistent with the binding energy of the neutral D 0 state of an arsenic donor. The second resonance shows a reduced charging energy due to the electrostatic coupling of the charged D ÿ state with electrodes. Excited states and Zeeman splitting under magnetic field present large energies potentially useful to build atomic scale devices. DOI: 10.1103/PhysRevLett.97.206805 PACS numbers: 73.21.ÿb, 61.72.Vv Dopant atoms are essential in semiconductor technology since they provide extrinsic charges necessary to create devices such as diodes and transistors. Nowadays the size of these electronic devices can be made so small than the discreteness of doping can influence their electrical properties [1]. On the other hand, it may be an important breakthrough if a dopant could be used as the functional part of a device instead of just providing charges. As an example, dopant-based spin qubits in silicon are possible candidates for quantum computation [2,3] thanks to their longer spin coherence time [4] as compared to twodimensional quantum dots defined by top gates in III=V heterostructures [5,6]. Although dopants are well known in bulk semiconductors, specific questions arise in the context of nanoscale devices like the reduced lifetime of the twoelectron state under electric field involved by readout schemes of spin qubits [7]. The aim of this work is to study the electronic states of single dopants in gated silicon nanostructures to bring information useful for these issues.Electron tunneling through isolated impurities has been observed previously in two-terminal devices such as GaAs= Al; Ga As double barrier heterostructures [8,9]. Here we present experimental results on electron transport through the localized states of individual n-type dopants in silicon nanowires. In contrast to previous studies, our devices have a three-terminal configuration with source, drain, and gate electrodes allowing a detailed investigation of charge, orbital, and spin states. In particular, we observe both the neutral D 0 and negatively charged D ÿ states, and compare their binding energy with the case of bulk dopants. This work provides a quantitative description of the electronic properties of a single dopant connected to electrodes in a gated nanostructure. This is the first transport experiment measuring the charge states of a real atomic system with a 1=r attracting Coulomb potential, thus very different from quantum dots with harmonic potentials.Our devices are 60 nm tall crystalline silicon wires (fins) with large contacts patterned by 193 nm optical lithography and ...

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confidence: 76%

Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire

et al. 2006

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“…The observation of similar dot widths of a few nanometers for different fin widths of hundreds of nanometers is consistent with the idea of a dot located at the edge of the fin and thus with the corner effect. 3,4 In addition to a large charging energy E c = ␣e⌬V G , these dots also have a large quantum level spacing ⌬E, as can be deduced from the temperature dependence of the conductance peaks in Fig. 3͑c͒.…”

Section: -mentioning

confidence: 91%

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

Sellier

Lansbergen

Caro

et al. 2007

Applied Physics Letters

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The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50ϫ 60ϫ 35 nm 3 . Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2476343͔ Nonplanar field-effect transistors called FinFETs ͑Ref. 1͒ are currently being developed to solve the problematic issues encountered with the standard planar geometry when the channel length is reduced to a sub-100 nm size. Their triplegate geometry is expected to have a more efficient gate action and to solve the leakage problem through the body of the transistor, one of the dramatic short channel effects. 2 However, their truly three-dimensional ͑3D͒ structure makes doping-and thus also potential-profiles very difficult to simulate and to understand using the current knowledge on device technology. Transport studies at low temperature, where the thermally activated transport is suppressed, can bring insight to these questions by measuring local gate action. For this reason we experimentally investigate the potential profile by conductance measurements and observe the formation of a subthreshold channel at the edge of the silicon nanowire. This corner effect has been proposed 3,4 as an additional contribution to the subthreshold current in these 3D triple-gate structures, where the edges of the nanowire experience stronger gate action due to the geometric enhancement of the field. However, besides extensive simulation work 3,4 -keeping in mind the difficulties with these 3D structures-very little experimental work has been published until now on this effect. 5 The FinFETs discussed here consist of a narrow singlecrystalline silicon wire with two large contact pads etched in a p-type silicon on insulator layer doped with 10 18 cm −3 boron atoms. This silicon wire is covered with a t ox = 1.4 nm thick thermal oxide and a second narrow polycrystalline silicon wire crossing the first one is fabricated to form a gate that surrounds the wire on three faces ͓Fig. 1͑a͔͒. The entire surface is then implanted with 10 19 cm −3 arsenic atoms to form n-type degenerate source, drain, and gate. During this implantation the wire located below the gate is protected and remains p type. In the investigated device series the height of the fin wire is H = 60 nm, while the width ranges from W =35 nm to 1 m and the gate length ranges from L =50 nm to 1 m. The relatively high p-type doping of the channel wire is chosen to ensure a depletion...

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“…Delay is better figure of merit, since it takes into account the capacitance associated with the structure as well as the current drivability. [22,23] The delay associated with inverter, T d is given by the equation T d = C gg *V DD /I ON , where C gg is the total gate capacitance which can be obtained by the CV sweep of the devices and V DD is the supply voltage (1 volt). We have calculated the rise time delay (T rd ) with respect to on current of the P-device and fall time delay (T fd ) with respect to the on current of the N-device in each case of variation.…”

Section: Resultsmentioning

confidence: 99%

Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

Prathima¹,

Bailey²,

Gurumurthy

2012

VLSICS

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A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (I OFF ), while reducing the fin height was beneficial in reducing the gate leakage current (I GATE ). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current

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Suppression of corner effects in triple-gate MOSFETs

Cited by 119 publications

References 6 publications

Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire

Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

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