Suppression of CoSix Induced Leakage Current Using Novel Capping Process for Sub-0.10um node SRAM Cell Technology

Abstract

We present a novel capping process for sub-0.10um node SRAM cell to suppress the Co silicide induced leakage current. The dimensions in the SRAM cell are scaled down to sub-0.10um. As a result, the CoSix induced leakage current increases as the sizes of the contact and the active area decrease due to the CoSix defects and the contact etch induced CoSix pitting. The double stacked layers on Co silicide successfully reduced the junction leakage current and widened the borderless contact etching process window by suppression of the CoSix defects and the Co silicide pittings.