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In order to develop high density NAND Flash device, the increased number of cell strings for 1 pag e buffer f orces to _ form a long bit-line with low sheet resistance, as well as low SitD parasitic capacitance between bit-lines. In this paper, we D secured a copper damascene process to form 38nm bit-lines(1) Photo Resist patterning with 76nm pitch using SADP (Self-Aligned Double Patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND Flash device with 38nm node technology.

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