No abstract

No abstract

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate FowlerNordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si SiO 2 interface during the FG dry-etching, prior to the backend processes such as metal-or via-etch. Index Terms-Flash memory, Fowler-Nordheim (FN) tunneling, over-erase, plasma damage.

We present our study on the dependence of data retention characteristics on the threshold voltage (V TH ) of the cell transistor revealing the combined effect of control gate voltage and cell transistor architecture. Data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim (FN) stress mainly occurs in tunnel oxide away from the region where maximum cell on-current flows. In the sub-50-nm region, due to short distance between the control gate and the shallow-trench isolation (STI) corner, the maximum cell on-current position is shifted from the STI corner to the channel center as control gate voltage decreases. The edge-thin tunnel oxide cell transistor, of which cell on-current flow is separated from tunneling current in negative cell V TH , shows 0.12-V superior data retention characteristic than the edge-thick tunnel oxide cell transistor at −3 V of cell transistor V TH in experiment.

We present this letter on the combining effect of tunnel-oxide degradation and narrow width effect on the data retention characteristics of NAND Flash memory cells. Due to severe boron segregation in shallow-trench isolation (STI) corner, the cell transistor suffers from intense V TH shift on STI corner in data retention mode. Independent of enhancing the tunnel-oxide quality, the data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim stress mainly occurs in tunnel oxide away from STI corner. Experimental results show that V TH shift is reduced by 0.3 V or more in retention mode as the tunneling is separated from the isolation edge.