Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays

Park, Min-Cheol; Kim, Keonsoo; Park, Jong-Ho; Choi, Jaehyuk

doi:10.1109/led.2008.2009555

Cited by 80 publications

(28 citation statements)

References 7 publications

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“…The target memory technology is the first parameter to consider when designing a native flash file system. The continuous technology downscaling strongly affects the reliability of the flash memory cells, while the reduction of the distance among cells may lead to several types of cell interferences (Jae-Duk et al, 2002;Mincheol et al, 2009). From the technology standpoint, two main families of flash memories do exist: (i) NOR flash memories and (ii) NAND flash memories.…”

Section: Flash Memory Issues and Challengesmentioning

confidence: 99%

Design Issues and Challenges of File Systems for Flash Memories

Carlo¹,

Fabiano²,

Prinetto³

et al. 2011

Flash Memories

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The increasing demand for high-speed storage capability both in consumer electronics (e.g., USB flash drives, digital cameras, MP3 players, solid state hard-disks, etc.) and mission critical applications, makes NAND flash memories a rugged, compact alternative to traditional mass-storage devices such as magnetic hard-disks. The NAND flash technology guarantees a non-volatile high-density storage support that is fast, shock-resistant and very power-economic. At higher capacities, however, flash storage can be much more costly than magnetic disks, and some flash products are still in short supply. Furthermore, the continuous downscaling allowed by new technologies introduces serious issues related to yield, reliability, and endurance of these devices (

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Section: Flash Memory Issues and Challengesmentioning

confidence: 99%

Design Issues and Challenges of File Systems for Flash Memories

Carlo¹,

Fabiano²,

Prinetto³

et al. 2011

Flash Memories

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show abstract

“…ECCs with programmable correction capability are now widely implemented in the same flash controller to adapt the error rate changes over program and erase cycles. This trend is confirmed by an increased number of publications proposing hardware implementations of adaptable BCH and RS codecs for NAND flash that guarantee low hardware overhead compared to worst-case designs that implement a fixed correction capability [Song et al 2002;Atieno et al 2006;Chen et al 2009;Caramia et al 2010;Cherukuri 2010;Zambelli et al 2012;Fabiano et al 2013]. However, for a realistic application of an adaptable ECC to a NAND flash, a strategy to decide which correction capability to use at runtime is required.…”

Section: Introductionmentioning

confidence: 96%

“…As NAND flash technology scales down and increases the number of levels per cell, system management algorithms need to face serious issues to maintain product reliability, while continuing to address reduced endurance and demand for increased performance [Li and Quader 2013;Micheloni et al 2010;Ielmini 2009;Jae-Duk et al 2002;Mincheol et al 2009;Cooke 2007]. Designers use error correction code (ECC) to guarantee target reliability levels by providing multiple-bit corrections to stored data [Li and Quader 2013].…”

Section: Introductionmentioning

confidence: 99%

Flares

Carlo

Galfano

Indaco

et al. 2014

ACM Trans. Archit. Code Optim.

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With the advent of solid-state storage systems, NAND flash memories are becoming a key storage technology. However, they suffer from serious reliability and endurance issues during the operating lifetime that can be handled by the use of appropriate error correction codes (ECCs) in order to reconstruct the information when needed. Adaptable ECCs may provide the flexibility to avoid worst-case reliability design, thus leading to improved performance. However, a way to control such adaptable ECCs' strength is required. This article proposes FLARES, an algorithm able to adapt the ECC correction capability of each page of a flash based on a flash RBER prediction model and on a measurement of the number of errors detected in a given time window. FLARES has been fully implemented within the YAFFS 2 filesystem under the Linux operating system. This allowed us to perform an extensive set of simulations on a set of standard benchmarks that highlighted the benefit of FLARES on the overall storage subsystem performances.

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“…As the technology node scales down, NAND Flash storage density increases with unavoidable reliability degradation. The main reliability issues of NAND Flash consist of data retention [1], program disturb [2], cell to cell interference [3], read disturb [4] et al Data retention error is the dominant error source among these reliability issues. One of the effective ways to deal with data retention error is to apply ECC (error correction code) [5].…”

Section: Introductionmentioning

confidence: 99%

Word line interference based data recovery technique for 3D NAND Flash

Huo

Liu

Cao

et al. 2018

IEICE Electron. Express

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When the NAND Flash memory is used beyond specific retention time, data stored in NAND Flash memory may not be read out correctly due to retention error. In this paper, a word line interference (WI) based data recovery technique is proposed to recover retention-failed data. By using WI, a large amount of electrons can be re-injected into retention-failed cells with one program operation. To improve recovery efficiency and recover retention error in a block, an iterated WI recovery algorithm which combines WI and previously reported DRRP technique is proposed. Experiment results show that WI recovery technique gains a higher recovery efficiency compared with DRRP technique.

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Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays

Cited by 80 publications

References 7 publications

Design Issues and Challenges of File Systems for Flash Memories

Design Issues and Challenges of File Systems for Flash Memories

Flares

Word line interference based data recovery technique for 3D NAND Flash

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