Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology

Koh, K.; Hwang, B.J.; Kwak, Kyung Won; Son, Yong; Lee, J.Y.; Jang, Jae Hoon; Seo, Sang‐Hun; Kim, H.S.; Park, D.; Kim, K.N.

doi:10.1109/vtsa.2003.1252553

Cited by 6 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Researchers have put forth a number of leakage power reduction strategies at the device, circuit, and architectural stages. By scaling the channel length, junction depth, and oxide layer at the device level, the leakage power is decreased [8][9][10]. Researchers have developed fresher transistor structures, such as the Fin-shaped FET (FINFET), which has two or more gates and reduces the subthreshold leakage current and the short channel effect.…”

Section: Leakage Current Minimization Methodologiesmentioning

confidence: 99%

Design of a 6t Sram Cell With Minimal Power Using Cadence Virtuoso

R.Nirmal¹,

P.Nithila²,

K.Jayasudha³

et al. 2023

DRSR

View full text Add to dashboard Cite

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

show abstract

Section: Leakage Current Minimization Methodologiesmentioning

confidence: 99%

Design of a 6t Sram Cell With Minimal Power Using Cadence Virtuoso

R.Nirmal¹,

P.Nithila²,

K.Jayasudha³

et al. 2023

DRSR

View full text Add to dashboard Cite

show abstract

“…Various leakage power reduction techniques have been proposed by researchers at the device, circuit, and architectural levels. At device level the leakage power is reduced by scaling the channel length, junction depth, oxide thickness [8][9][10].…”

Section: ░ 3 Leakage Current Reduction Techniquesmentioning

confidence: 99%

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Banu

Gupta

2022

IJEER

View full text Add to dashboard Cite

Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

show abstract