No abstract

This study aimed to determine the effects of the binaural beat (BB) on brainwave induction using an inaudible baseline frequency outside the audible frequency range. Experiments were conducted on 18 subjects (11 males [mean age: 25.7 ± 1.6 years] and 7 females [mean age: 24.0 ± 0.6 years]). A BB stimulation of 10 Hz was exerted by presenting frequencies of 18,000 Hz and 18,010 Hz to the left and right ears, respectively. A power spectrum analysis was performed to estimate the mean of the absolute power of the alpha frequency range (8–13 Hz). The variation in the mean alpha power during the rest and stimulation phases in each brain area was compared using the Wilcoxon signed-rank test. Compared to the rest phase, the stimulation phase with BB showed an increasing trend in the mean alpha power across all 5 brain areas. Notably, a significant increase was found in the frontal, central, and temporal areas. This is a significant study in that it determines the effects of only BB without the influence of auditory perception, which has been overlooked in previous studies.

High performance poly-Si thin film transistors were fabricated by using a new crystallization method, Metal-Induced Lateral Crystallization (MILC). The process temperature was kept below 500°C throughout the fabrication. After the gate definition, thin nickel films were deposited on top of the TFT's without an additional mask, and with a one-step annealing at 500°C, the activation of the dopants in source/drain/gate a-Si films was achieved simultaneously with the crystallization of the a-Si films in the channel area. Even without a post-hydrogenation passivation, mobilities of the MILC TFT's were measured to be as high as 120cm2/Vs and 90cm2/Vs for n-channel and p-channel, respectively. These values are much higher than those of the poly-Si TFT's fabricated by conventional solid-phase crystallization at around 6001C.

We have realized 4 6 9 SRAM cell size of 0.294um2 with 80nm technology and the single stack 9 cell technology. SSTFT and vertical node contacts are major keys in the s' cell technology. The stacked single crystal silicon thin film is developed for load PMOS SSTFT of the s' SRAM cell. The load PMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64M-bits SRAM is achieved by this S3 cell technology. Basic reliability of SSTFT with 80nm length is also investigated in this study. IntroductionThere have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T full CMOS S U M had been continued as the technology advances as shown in Fig.1. However, conventional 6T full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a Si-substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T full CMOS SRAM is 70-90p, which is too large compared to 8 -9 p of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maTimurn density is 72M-bits at the most [l]. Therefore, pseudo SRAM or IT SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high-density SRAM applications more than 64M-bits. However, the refresh function is indispensable for the pseudo SRAM. The refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand-by current, random access time. For this reason, if the chip size penalty of 6T full CMOS SRAM is overcame, SRAM would have a sufficient competitiveness compared to DRAM cell based pseudo SRAM. In the past, TFT (Thin Film Transistor) load SRAM cell had been widely used for low power and relatively slow applications as one alternative of 6T full CMOS SRAM for saving the cell size. However, the T I T load cell could not meet the demand of lower operation voltages, such as less than 3.0V mainly due to the very poor electrical characteristics. The poor characteristics were resulted from the polycrystalline Si thin films and relatively thick low quality gate oxide. F--1'-I 1 1 -1 0.01 0.0 ai 0.2 0.3 0.4 0.5 0.8 Design Rule(um) Fig. 1 SRAM cell size trend vs. design rule In order to overcome both of the size penalty of the conventional 6T full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S' cell [Z]. The schematic circuit diagram of single stack S' cell is shown in Fig2. The load PMOS SSTFT on ILD has nearly single crystal silicon channel according to TEM and electron diffraction pattern analysis as shown in Fig 3. In this study, we present the 46F2 single stack S' SRAM cell technology with 8Gnm design rule in further detail, including the process integration and the basic reliability characteristics of SSTFT. I vcc B/L BIL Fig. 2: Schematic circuit diagram of single stack S3 Cell.