Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

Kang, Young-Tae; Jung, Soon‐Moon; Jang, Jae Hoon; Moon, Joo-Tae; Cho, W.S.; Yeo, Chadong; Kwak, Kyung Won; Choi, Beohmrock; Hwang, B.J.; Jung, Woojin; Kim, Seung Ju; Kim, Kee Joo; Na, J.H.; Lim, Hyun Suk; Jeong, Jae−Hun; Kim, K.

doi:10.1109/soi.2004.1391586

Cited by 3 publications

(2 citation statements)

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“…Availability of such technologies makes it possible to partition the cache at the granularity of individual cache cells [Kang et al 2004]. However, wafer bonding requires fewer changes in the manufacturing process and is more popular in industry [Mayega et al 2003;Lee et al 2000] than MLBS technology.…”

Section: D Integration Technologiesmentioning

confidence: 99%

Design space exploration for 3D architectures

Xie

Loh

Black

et al. 2006

J. Emerg. Technol. Comput. Syst.

271

150

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As technology scales, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. Increasing interconnect costs make it necessary to consider alternate ways of building modern microprocessors. One promising option is 3D architectures where a stack of multiple device layers with direct vertical tunneling through them are put together on the same chip. As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures. In this article, we give a brief introduction to 3D integration technology, discuss the EDA design tools that can enable the adoption of 3D ICs, and present the implementation of various microprocessor components using 3D technology. An industrial case study is presented as an initial attempt to design 3D microarchitectures.

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Section: D Integration Technologiesmentioning

confidence: 99%

Design space exploration for 3D architectures

Xie

Loh

Black

et al. 2006

J. Emerg. Technol. Comput. Syst.

271

150

View full text Add to dashboard Cite

show abstract

“…The main advantages of 3D integration over 2D implementation are in high device density, novel integration opportunities, optimal routing, lower power needs per device, and shortened global interconnections. Two of the more recent wafer-scale 3D integration technology approaches include a 'sequential processing,' an approach where silicon device layer is grown, crystallized or transferred onto a host substrate with completed circuits [ 1,3,6,7], and 'parallel processing,' where the wafers are independently fabricated in parallel and integrated in the back-end by wafer bonding [2, 4, 51. The main deficiency in 3D sequential processing is the requirement of high thermal budget fabrication steps to complete the circuits subsequent to the creation of the upper silicon layer.…”

mentioning

confidence: 99%

Low temperature wafer-scale 3D ICs: technology and characteristics

Kim

Tiwari

2005

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

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Absfruci -Fabrication techniques that allow wafer-scale transplantation, bonding and interconnecting of fully fabricated device layers with thickness on the order of micrometers are described. The temperature budget of this 3D integration technology is less than 350 'C and the approach utilizes Benzocydobutenc (BCB) as the permanenl wafer bonding medium. Alignment registration of several micrometers between donor device layer to the host substrate is achieved. The characterization of devices, structures and process conditions are presented. Also, measurement of heating effects and temperatures in a 3D IC environment is described. The 3D integration approach allows reduction in crosstalk for mixed-signal applications using inter-device layer ground planes. This technique shows -8 dB of crosstalk attenuation between device layers. The newly developed 39 integration fabrication methodology can be extended beyond silicon-based devices to SiCe and 111-1V technologies.

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