3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional microarchitecture between two die in a stack.Results: It is shown that a 32MB 3D stacked DRAM cache can reduce the cycles per memory access of a twothreaded RMS benchmark on average by 13% and as much as 55% while increasing the peak temperature by a negligible 0.08ºC. Off-die BW and power are also reduced by 66% on average. It is also shown that a 3D floorplan of a high performance microprocessor can simultaneously reduce power 15% and increase performance 15% with a small 14ºC increase in peak temperature. Voltage scaling can reach neutral thermals with a simultaneous 34% power reduction and 8% performance improvement.

Injury-induced sensitization of nociceptors contributes to pain states and the development of chronic pain. Inhibiting activity-dependent mRNA translation through mechanistic target of rapamycin and mitogen-activated protein kinase (MAPK) pathways blocks the development of nociceptor sensitization. These pathways convergently signal to the eukaryotic translation initiation factor (eIF) 4F complex to regulate the sensitization of nociceptors, but the details of this process are ill defined. Here we investigated the hypothesis that phosphorylation of the 5Ј cap-binding protein eIF4E by its specific kinase MAPK interacting kinases (MNKs) 1/2 is a key factor in nociceptor sensitization and the development of chronic pain. Phosphorylation of ser209 on eIF4E regulates the translation of a subset of mRNAs. We show that pronociceptive and inflammatory factors, such as nerve growth factor (NGF), interleukin-6 (IL-6), and carrageenan, produce decreased mechanical and thermal hypersensitivity, decreased affective pain behaviors, and strongly reduced hyperalgesic priming in mice lacking eIF4E phosphorylation (eIF4E S209A ). Tests were done in both sexes, and no sex differences were found. Moreover, in patch-clamp electrophysiology and Ca 2ϩ imaging experiments on dorsal root ganglion neurons, NGF-and IL-6-induced increases in excitability were attenuated in neurons from eIF4E S209A mice. These effects were recapitulated in Mnk1/2 Ϫ/Ϫ mice and with the MNK1/2 inhibitor cercosporamide. We also find that cold hypersensitivity induced by peripheral nerve injury is reduced in eIF4E S209A and Mnk1/2 Ϫ/Ϫ mice and following cercosporamide treatment. Our findings demonstrate that the MNK1/2-eIF4E signaling axis is an important contributing factor to mechanisms of nociceptor plasticity and the development of chronic pain.

As technology scales, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. Increasing interconnect costs make it necessary to consider alternate ways of building modern microprocessors. One promising option is 3D architectures where a stack of multiple device layers with direct vertical tunneling through them are put together on the same chip. As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures. In this article, we give a brief introduction to 3D integration technology, discuss the EDA design tools that can enable the adoption of 3D ICs, and present the implementation of various microprocessor components using 3D technology. An industrial case study is presented as an initial attempt to design 3D microarchitectures.

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This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either face-to-face or face-to-back in order to construct the 3D structure. In this work a face-to-face bonding is utilized because it yields a higher density dieto-die inter-connect than is possible with face-to-back. With sufficiently dense die-to-die interconnect devices as complex as an iA32 microprocessor can be repartitioned or split between two die in order to simultaneously improve performance and power.The 3D structure of this emerging technology is examined and applied in this paper to a real x86 deeply pipelined high performance microprocessor. In this initial study, it is shown that a 3D implementation can potentially improve the performance by 15% while improving power by 15%.