Die Stacking (3D) Microarchitecture

Abstract

3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional microarchitecture between two die in a stack.Results: It is shown that a 32MB 3D stacked DRAM cache can reduce the cycles per memory access of a twothreaded RMS benchmark on average by 13% and as much as 55% while increasing the peak temperature by a negligible 0.08ºC. Off-die BW and power are also reduced by 66% on average. It is also shown that a 3D floorplan of a high performance microprocessor can simultaneously reduce power 15% and increase performance 15% with a small 14ºC increase in peak temperature. Voltage scaling can reach neutral thermals with a simultaneous 34% power reduction and 8% performance improvement.

Leveraging 3D Technology for Improved Reliability

“…The modeling parameters and thermal constants for each layer are as described in [2,26] and reproduced in Table 3. The heat sink is placed close to the bottom Table 3.…”

“…We execute the 3D processor at a lower voltage and frequency than the 2D baseline processor until its average peak temperature matches that of the baseline. Similar to the methodology in [2], we assume that voltage and frequency scale linearly for the voltage ranges considered here. We observed that a 3D processor with a 7 W checker (15 W checker) operating at a frequency of 1.9 GHz (1.8 GHz) has the same thermal characteristics as a 2D baseline processor operating at a frequency of 2 GHz.…”

Self-related traces: An alternative to full-system simulation for NoCs

“…Coherence between L1 and L2 caches is kept using a directory-based MOESI protocol. We assume 3D-stacking [11], and therefore, each node in the CMP has a memory controller. Regarding the on-chip network, we use a mesh topology which has all the links among nodes of the same size and width.…”

Fine grain 3D integration for microarchitecture design through cube packing exploration

“…Recently, this kind of exploration is used for performance improvement by Black et.al. in [29]. However this study is limited to single-layer blocks.…”