Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Pepe, Federico; Bonfanti, Andrea; Levantino, Salvatore; Samori, Carlo

doi:10.1109/jssc.2013.2273181

Cited by 57 publications

(38 citation statements)

References 29 publications

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“…For this inductor-based F 2 tank, R p2 /R p1 = 0.25, and the condition in (18) is satisfied for Q 0 < 15. Furthermore, in the CM excitation, the currents in adjacent windings have opposite direction, which results in an increased ac resistance [27], and so the Q-factor of the CM inductance is even smaller than in (20). The Q-factor of L CM inductance of Fig.…”

Section: A Inductor-based F 2 Tankmentioning

confidence: 99%

“…16(b)]. Table I compares its performance with the original class-D oscillators (as well as other state-of-the-art oscillators [20], [25], [31] aimed at reducing the 1/f noise upconversion). Compared with the original design, the FoM at 10 MHz offset is degraded in the class-D/F 2 oscillator by 3 dB, mainly due to the lack of ultrathick metal layers, which lowers the inductor's Q.…”

Section: A Class-d/f 2 Oscillatormentioning

confidence: 99%

“…The concept of a harmonically rich tank current degrading the close-in oscillator spectrum has been noticed for quite some time; however, the proposed solutions mostly include the linearization of the system to reduce the level of current harmonics by limiting the oscillation amplitude by an AGC [16], [17], or the linearization of gm-devices [18], [19], at the expense of the oscillator's startup margin and increased 1/f 2 PN. In a completely different strategy, a resistor is added in [20] in series with gm-device drains. An optimum value of the resistor minimizes the flicker noise upconversion; however, the 1/f noise improvement is at the expense of the 20 dB/decade degradation in oscillators with low V DD and high current consumption.…”

mentioning

confidence: 99%

See 2 more Smart Citations

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

Shahmohammadi

Babaie

Staszewski

2016

IEEE J. Solid-State Circuits

143

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Section: A Inductor-based F 2 Tankmentioning

confidence: 99%

Section: A Class-d/f 2 Oscillatormentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

Shahmohammadi

Babaie

Staszewski

2016

IEEE J. Solid-State Circuits

143

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“…Several 1/f 3 phase noise (PN) reduction mechanisms have been identified [2]- [4]. Pepe et al [2] demonstrated that introducing an additional phase shift between drain and gate of the cross-coupled pair can suppress the 1/f noise upconversion.…”

Section: Introductionmentioning

confidence: 99%

Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators

Siriburanon

Staszewski

2019

IEEE Trans. Circuits Syst. II

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This brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis (PAC or PXF), which is a key tool in understanding the flicker noise upconversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed.

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“…Removing the tail current transistor eliminates its noise effect and increase the oscillation amplitude with relaxed start-up condition [7]. However in this structure increased oscillation amplitude causes the cross-coupled transistors to leave the saturation and enter into triode region.…”

Section: Introductionmentioning

confidence: 99%

Low-phase-noise CMOS VCO with new drain–gate feedback path

Rezaei

Jannesari

2016

Analog Integr Circ Sig Process

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In this paper a new LC oscillator without tail current source with an impedance transformation block (ITB) has been presented. Using this ITB, the noise generation from active devices is reduced. The cross-coupled transistors remain mostly in the saturation region and prevent decreasing of LC-tank quality factor. Moreover this structure benefits from more relaxed start-up condition as compared to the conventional LC oscillators and preserves its low phase-noise performance even in low voltage operation. This oscillator is designed and simulated in 0.18 lm CMOS process. The simulation results show that the proposed oscillator achieved a phase noise between -138.5 and -141.2 dBc/Hz at 3 MHz frequency offset with 23 % tuning range between 4.61 and 5.79 GHz. The corresponding Figure-of-merit in this tuning range is between -189.1 and -192.1 dBc/Hz which is among the best reported performance in comparison to the other state of the arts designs.

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Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Cited by 57 publications

References 29 publications

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators

Low-phase-noise CMOS VCO with new drain–gate feedback path

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