Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al
            <sub>2</sub>
            O
            <sub>3</sub>
            formed by thermal oxidation of evaporated aluminium

Taking, S.; Banerjee, Abhishek; Zhou, Haiping; Li, X.; Khokhar, Ali Z.; Oxland, R.; McGregor, Ian A.; Bentley, Steven; Rahman, Faiz; Thayne, Iain; Dabiran, A. M.; Wowchak, A. M.; Cui, B.; Wasige, Edward

doi:10.1049/el.2010.2781

Cited by 22 publications

(10 citation statements)

References 6 publications

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“…It is clear that a 20-sec Al etch has a significant impact on the device performance with the drain current at zero gate voltage (I DSS ) more than double that of a device in which the etching time was 10 secs. Compared to similar results for the AlN/GaN HEMT (unprotected and unpassivated device in Figure 6(b)) on the same epilayer structure, these results show that protecting and passivating the AlN/GaN layers during processing yield AlN/GaN MOS-HEMT with far superior and excellent transistor characteristics [6].…”

Section: Gate Wrap-around Mos-hemt Optimisationsupporting

confidence: 67%

“…A new process for the fabrication AlN/GaN-based devices was therefore developed. It involved employing thermally grown Al 2 O 3 for protection of the very sensitive AlN epilayer from exposure to liquid chemicals during processing [6] as earlier described for TLM experiments (Figure 2). This Al 2 O 3 , which is formed by thermal oxidation of evaporated Al, acts as a surface passivate and as a gate dielectric for the transistors.…”

Section: Gate Wrap-around Mos-hemt Optimisationmentioning

confidence: 99%

“…Despite the demonstrated potential, problems such as surface sensitivity [6], high leakage current [7], and high contact resistance [3,7] have limited the performance and reliability of these devices. Several techniques have been reported to overcome these problems.…”

Section: Introductionmentioning

confidence: 99%

“…The devices discussed here employ thermally grown Al 2 O 3 as a gate dielectric and surface passivation [6]. This approach provides an opportunity to define the Ohmic contact areas by wet etching of Al (and optimisation of this processing step) prior to the formation of Al 2 O 3 and Ohmic metal deposition [9].…”

Section: Introductionmentioning

confidence: 99%

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AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

Taking

MacFarlane

Wasige

2011

Active and Passive Electronic Components

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Process development of AlN/GaN MOS-HEMTs is presented, along with issues and problems concerning the fabrication processes. The developed technology uses thermally grown Al 2 O 3 as a gate dielectric and surface passivation for devices. Significant improvement in device performance was observed using the following techniques: (1) Ohmic contact optimisation using Al wet etch prior to Ohmic metal deposition and (2) mesa sidewall passivation. DC and RF performance of the fabricated devices will be presented and discussed in this paper.

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Section: Gate Wrap-around Mos-hemt Optimisationsupporting

confidence: 67%

Section: Gate Wrap-around Mos-hemt Optimisationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

Taking

MacFarlane

Wasige

2011

Active and Passive Electronic Components

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“…Perhaps for this reason, as well as application-driven thermal requirements, published HEMT substrate thicknesses have been reported as thin as 25 µm for CVD diamond, 100 µm for SiC, to even 1 mm for silicon [4,18,21]. Published material also has a wide range of GaN thicknesses for application-driven electrical, and perhaps thermal requirements, ranging from 0.47 µm to 3.8 µm and even up to 9 µm [21][22][23].…”

Section: Figure 2: (A) Gan Hemt Device (Not To Scale) (B) Simplified mentioning

confidence: 99%

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

Nochetto

Jankowski

Bar‐Cohen

2011

Volume 10: Heat and Mass Transport Processes, Parts a and B

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The present work uses finite element thermal simulations of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) to evaluate the impact of device design parameters on the junction temperature. In particular the effects of substrate thickness, substrate thermal conductivity, GaN thickness, and GaN-to-substrate thermal boundary resistance (TBR) on device temperature rise are quantified. In all cases examined, the TBR was a dominant factor in overall device temperature rise. It is shown that a TBR increase can offset any benefits offered through a more conductive substrate and that there exists a substrate thickness independent of TBR which results in a minimum junction temperature. Additionally, the decrease of GaN thickness only provides a thermal benefit at small TBRs. For TBRs on the order of 10 -4 cm 2 K/W or greater, decreasing the GaN thickness can actually increase the temperature as the heat from the highly localized source is not sufficiently spread out before crossing the GaN-substrate boundary. The tradeoff between GaN heat spreading, substrate heat spreading, and temperature rise across the TBR results in a GaN thickness with minimum total temperature rise. For the TBR values of 10 -4 cm 2 K/W and 10 -3 cm 2 K/W these GaN thicknesses are 0.8 µm and 9 µm respectively.Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it Same asReport (SAR) 18. NUMBER OF PAGES 9 19a. NAME OF RESPONSIBLE PERSON a. REPORTunclassified b. ABSTRACT unclassified c. THIS PAGE unclassified Standard Form 298 (Rev. 8-98)

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Preparation of ultrathin polydimethylsiloxane-coating on Cu as oxidation-protection layer

Kim

Jeong

Seo

et al. 2012

Applied Surface Science

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Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al ₂ O ₃ formed by thermal oxidation of evaporated aluminium

Cited by 22 publications

References 6 publications

AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

Preparation of ultrathin polydimethylsiloxane-coating on Cu as oxidation-protection layer

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Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al 2 O 3 formed by thermal oxidation of evaporated aluminium

Cited by 22 publications

References 6 publications

AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

Preparation of ultrathin polydimethylsiloxane-coating on Cu as oxidation-protection layer

Contact Info

Product

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Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al ₂ O ₃ formed by thermal oxidation of evaporated aluminium