This paper reports the analyses of the inductive degeneration, noise filter, and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. that the Hartley topology with inductive degeneration can lead potentially to a PN reduction up to 10 dB.Lastly, the results presented in [5] show that the 1/f 3 region of the PN extends above a 1 MHz frequency offset for the Hartley oscillator circuit topology under study. This can be attributed to the adoption of nanoscale CMOS technologies characterized by flicker noise corners of several tens or hundreds of MHz, which lead to flicker noise upconversion being responsible for most of the PN even at large offsets from the carrier frequency. Thereby, the optimum inductance value for the total PN shown in Figure 5 is very close to that given by (7)-(9), because at a 1 MHz offset, thermal noise has a negligible effect on PN.
NOISE FILTERIn this section, we will derive the analytical expression for the oscillation frequency (f 0 ) of a Hartley oscillator circuit topology in which we introduced a noise band-stop filter (L 4 , C 4 ) to the source node of M 1 as shown in Figure 7(a). Because of its noise filtering action, it is referred therein [8] as noise filter. Moreover, we will observe that there is an optimum inductance value (L 4 ) for which the Figure 7. (a) Hartley oscillator circuit topology...