Survey on chiplets: interface, interconnect and integration methodology

Ma, Xiaohan; Wang, Ying; Wang, Yujie; Cai, Xuyi; Han, Yinhe

doi:10.1007/s42514-022-00093-0

Cited by 30 publications

(4 citation statements)

References 39 publications

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“…35 The integration leads toward the other advantage of this system, which will be the parallelization of several chips, in a chiplet configuration. [94][95][96] This chiplet configuration will further improve the performances, reaching over 100 TOPS/W when scaled to 16 chips. The last piece of the puzzle is the integration of the activation function on the chip.…”

Section: Neural Network and Next Stepsmentioning

confidence: 99%

Design and testing of silicon photonic 4F system for convolutional neural networks

Peserico

Meng

Yang³

et al. 2023

Integrated Optics: Devices, Materials, and Technologies XXVII

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Convolution Neural Networks have raised as the key technology for most of the novel applications that appear in the last years. Convolution, the main operation that CNN has to perform, has a high computational cost, raising power consumption and latency, especially for large matrices. Optics and photonics can perform the same operation at virtual O(1) cost and speed-of-light latency, thanks to the properties of Fourier optics. In this paper, we will show the implementation of the main components and the modeling for non-idealities that might occur.

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Section: Neural Network and Next Stepsmentioning

confidence: 99%

Design and testing of silicon photonic 4F system for convolutional neural networks

Peserico

Meng

Yang³

et al. 2023

Integrated Optics: Devices, Materials, and Technologies XXVII

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“…Chiplet technology has emerged as a promising solution to this challenge, allowing multiple specialized chips to be integrated into a more extensive system. [1][2][3][4][5] This approach offers cost reduction, improved yield, shorter design cycles, and better integration. The die-to-die short-reach wireline communication link with high pin/energy efficiency is critical for chiplet technology, which can be applied to memory interconnects and electrical/optical (E/O) interfaces.…”

Section: Introductionmentioning

confidence: 99%

“…As the integrated‐circuit feature sizes approach the physical limit, the cost of realizing high‐performance system‐on‐chip (SOC) increases significantly. Chiplet technology has emerged as a promising solution to this challenge, allowing multiple specialized chips to be integrated into a more extensive system 1–5 . This approach offers cost reduction, improved yield, shorter design cycles, and better integration.…”

Section: Introductionmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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“…With the development of semiconductor manufacturing processes, Chiplet-based systems have been widely investigated to achieve the continuation of Moore’s law [ 1 , 2 , 3 ]. Due to the advantages of miniaturization, high performance, and low cost, Chiplet-based systems have been applied in computing systems and processing-in-memory systems [ 4 , 5 , 6 ]. Through silicon via (TSV) is a key technology to achieve vertical interconnection between different dies in Chiplet-based systems [ 7 , 8 , 9 , 10 , 11 ].…”

Section: Introductionmentioning

confidence: 99%

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Wang

Chen

et al. 2023

Micromachines

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In this research, an efficient thermal-stress coupling design method for a Chiplet-based system with a coaxial through silicon via (CTSV) array is developed by combining the support vector machine (SVM) model and particle swarm optimization algorithm with linear decreasing inertia weight (PSO-LDIW). The complex and irregular relationship between the structural parameters and critical indexes is analyzed by finite element simulation. According to the simulation data, the SVM model is adopted to characterize the relationship between structural parameters and critical indexes of the CTSV array. Based on the desired critical indexes of the CTSV array, the multi-objective evaluation function is established. Afterwards, the structural parameters of the CTSV array are optimized through the PSO-LDIW algorithm. Finally, the effectiveness of the developed method is verified by the finite element simulation. The simulated peak temperature, peak stress of the Chiplet-based system, and peak stress of the copper column (306.16 K, 28.48 MPa, and 25.76 MPa) well agree with the desired targets (310 K, 30 MPa, and 25 MPa). Therefore, the developed thermal-stress coupling design method can effectively design CTSV arrays for manufacturing high-performance interconnect structures applied in Chiplet-based systems.

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Survey on chiplets: interface, interconnect and integration methodology

Cited by 30 publications

References 39 publications

Design and testing of silicon photonic 4F system for convolutional neural networks

Design and testing of silicon photonic 4F system for convolutional neural networks

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

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