Survey on Coarse Grained Reconfigurable Architectures

Tehre, Vaishali; Kshirsagar, R. V.

doi:10.5120/7429-0104

Cited by 29 publications

(15 citation statements)

References 20 publications

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“…Most existing algorithms fall into one of several styles, including greedy algorithms, randomized algorithms, clustering algorithms, Integer Linear Programming, and Analytical Placement. Comprehensive discussion and further references can be found in the following surveys: (Tehre and Kshirsagar, 2012;Choi, 2011;Theodoridis et al, 2008;Hartenstein, 2001a,b). We provide a brief summary here.…”

Section: Mapping Algorithmsmentioning

confidence: 99%

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Sistla¹,

Patel²,

Mehta³

2015

HCj

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One of the grand challenges in the design of portable/wearable electronics is to achieve optimal efficiency and flexibility in a tiny low power package. Coarse grained reconfigurable architectures (CGRAs) hold great promise for low power, high performance, and flexible designs for a domain of applications. CGRAs are very promising due to the ability to highly customize such architectures to an application domain. However, greater customization makes the mapping of applications onto these architectures very challenging. Good tools and fast, effective mapping algorithms are needed to support design space exploration for CGRAs. In particular, the mapping problem has been difficult to solve in a satisfying and general way. In this paper, we present an architectural design flow using crowdsourcing to provide mappings of benchmarks onto new architectures. We show that the crowd can provide high quality, reliable mappings, significantly outperforming our custom Simulated Annealing algorithm in almost all cases. We further show that the crowd can provide other types of feedback that are difficult to obtain from an automatic mapping algorithm. Our proof of concept cross-architectural study supports an 8Way or 4Way1Hop architecture as a top choice, concludes that a custom modification that constrains inputs and outputs consumes less energy but requires more area than its less constrained counterpart, and suggests that Stripe architectures are interesting to consider because they perform nearly as well as our mesh variants and may present a more straightforward mapping problem for the crowd or an automatic mapping algorithm.

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Section: Mapping Algorithmsmentioning

confidence: 99%

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Sistla¹,

Patel²,

Mehta³

2015

HCj

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show abstract

“…When dealing with word-level compute-intensive applications, coarse-grained reconfigurable computing fabrics have substantial advantages in performance and power over instruction driven processors, while still possessing a very high function flexibility compared with the hardwired logic [1]. In contrast, fined-grained reconfigurable devices have more advantages in bit-level control-intensive computations.…”

Section: Introductionmentioning

confidence: 99%

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Liu

Wang

Chen

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 × 16 multi-functional processing elements (PEs), is used to accelerate computeintensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.

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“…[5][6][7] and [8]), reconfigurable on-chip communication fabrics (e.g. [9,10] and [11]), fault tolerance design (e.g.…”

Section: Introductionmentioning

confidence: 99%

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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Survey on Coarse Grained Reconfigurable Architectures

Cited by 29 publications

References 20 publications

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

A Survey on Reconfigurable System-on-Chips

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