Survey, taxonomy, and methods of QCA-based design techniques—part II: reliability and security

Abstract

Quantum-dot cellular automata is a new and adroit technology currently under extensive research for the post-CMOS era VLSI chip design. Quantum-dot cellular automata (QCA) has promised more reliable, fault-tolerant, and secure chip designs. Also, while analyzing the QCA circuits for power and energy dissipation, promising results have been reported that suggest that the QCA circuits dissipate significantly less energy and operate very close to the Shannon-von Neumann-Landauer (SNL) limit. Security is another concern that has led to the development of QCA based security systems like physically unclonable functions and true random number generators. In this paper, a survey of different fault-tolerant and QCA based security circuits has been provided, along with the discussion of critical design aspects and parameters in QCA technology.

Novel Ultra-Energy-Efficient Reversible Designs of Sequential Logic Quantum-Dot Cellular Automata Flip-Flop Circuits

“…This trade-off concept has been widely documented and used in VLSI integrated circuit design for meeting diverse system requirements [20,21]. The trade-off in terms of cell count, latency, energy dissipation, the number of layers used, fault tolerance, and reliability for several nonreversible digital designs to examine the efficiencies of QCA circuits has been well documented [22,23]. However, the trade-offs between reversible and nonreversible QCA designs have yet to be documented.…”

Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology

“…When any of the above-mentioned parameters are altered, several quantum effects result in decreased performance of a device at the nanoscale. Small feature sizes associated with current CMOS technology will have many limitations in the near future [1]. In addition to leakage currents, power dissipation and oxide thickness scaling can also result in electron migration and cross-talk [1,2].…”

“…Small feature sizes associated with current CMOS technology will have many limitations in the near future [1]. In addition to leakage currents, power dissipation and oxide thickness scaling can also result in electron migration and cross-talk [1,2]. There are several examples of DIBL (drain induced barrier lowering), a decrease in gate oxide thickness, the merging of source and drain that produces punch-through conditions, and excessive current flow from a physical perspective [1].…”

“…In addition to leakage currents, power dissipation and oxide thickness scaling can also result in electron migration and cross-talk [1,2]. There are several examples of DIBL (drain induced barrier lowering), a decrease in gate oxide thickness, the merging of source and drain that produces punch-through conditions, and excessive current flow from a physical perspective [1]. The effects mentioned above violate the laws of physics and hinder the device from working properly.…”

“…Since the number of components on a single chip is increasing, excessive heat is generated in the chip and the small size of the chip causes it to be difficult to remove. The chip is thus destroyed under operative conditions as a result of the power dissipation [1]. To combat the consequences and effects discussed above, CMOS in nano regime needs to adopt alternate paradigms.…”