Quantum-dot cellular automata (QCA) is a novel promising nanoscale technology that allows the design of integrated circuits with high speed, low power consumption, and high density. Because of this potential benefit, the QCA is chosen as a viable alternative to complementary metal oxide semiconductor (CMOS) technology. In this paper, we have provided a comprehensive review of various types of digital circuits and modules in QCA nanotechnology. We have discussed circuits like XOR/XNOR, half and full adder, multiplexers and demultiplexers, comparators, flip-flops, Arithmetic and Logical Unit (ALU) and Random-Access Memory (RAM). We have shown how these circuits are designed using various methodologies being it using different types of cross-overs, multi-layer designs or using cell-to-cell interaction method advantages and overheads. These logical circuits are compared on the basis of various parameters such as cell area, total area, latency, number of cells, energy dissipation, and complexity and are explained starting from the design which is having large cell count to the efficient design present in terms of the above parameters.

Quantum-dot cellular automata is a new and adroit technology currently under extensive research for the post-CMOS era VLSI chip design. Quantum-dot cellular automata (QCA) has promised more reliable, fault-tolerant, and secure chip designs. Also, while analyzing the QCA circuits for power and energy dissipation, promising results have been reported that suggest that the QCA circuits dissipate significantly less energy and operate very close to the Shannon-von Neumann-Landauer (SNL) limit. Security is another concern that has led to the development of QCA based security systems like physically unclonable functions and true random number generators. In this paper, a survey of different fault-tolerant and QCA based security circuits has been provided, along with the discussion of critical design aspects and parameters in QCA technology.

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.

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Quantum-dot cellular automata (QCA) technology is considered to be the future of nanoelectronic device fabrication technology. The fabrication density of the transistors in a particular area in the current nanoelectronic industry has saturated. Adroit alternate to current CMOS based VLSI technology is being researched upon. QCA technology is considered to be the noblest post-CMOS era fabrication technology. In this paper, novel energy-efficient QCA designs for 1/2 and 1/3 convolution encoders have been presented. Both the presented designs were proven to be efficient than previously designed circuits. The efficiency of the design is calculated for critical design parameters like cell count, cell area, latency (clock phases), complexity and energy dissipation. The proposed 1/2 convolution encoder uses 21 QCA cells consuming an area of 0.012µm2. The complexity of this design was calculated to be 2. The energy dissipation analysis revealed that the presented circuit dissipated 14.03meV of energy. The proposed 1/3 convolution encoder uses 32 QCA cells consuming an area of 0.025µm2. The energy dissipation analysis revealed that the presented circuit dissipated 16.88meV of energy. Both the proposed designs used only a few more extra cells than the previously designed circuits but induced stronger polarizations and were more fault-tolerant. It was found that the circuits proposed are 25% more energy efficient than previously designed circuits. The latency of the proposed designs was of 2 clock phases, thus making it suitable for high-speed operation. Significant improvement of the designs was done to optimize the circuit for secure nano-communication devices.