Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward

Kamuf, Matthias; Öwall, Viktor; Anderson, John B.

doi:10.1109/tcsii.2007.891753

Cited by 12 publications

(5 citation statements)

References 10 publications

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“…In the literature, the SMU can be designed in RE [8,11,12,14,15] and trace back (TB) [12,13] styles. The RE style has shorter latency and higher decoding speed than the TB style.…”

Section: Segment-based Vdmentioning

confidence: 99%

Power-efficient decoder implementation based on state transparent convolutional codes

Shiau

Yang

Chen

et al. 2012

IET Circuits Devices Syst.

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In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

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“…In the literature, the SMU can be designed in RE [8,11,12,14,15] and trace back (TB) [12,13] styles. The RE style has shorter latency and higher decoding speed than the TB style.…”

Section: Segment-based Vdmentioning

confidence: 99%

Power-efficient decoder implementation based on state transparent convolutional codes

Shiau

Yang

Chen

et al. 2012

IET Circuits Devices Syst.

View full text Add to dashboard Cite

show abstract

“…The register-exchange (RE) approach is chosen since the number of states is low. Since an additional subset signal memory is needed for TCM, the least overhead is introduced since the decoding latency is the lowest compared to trace-back architectures, which have a least twice the latency [8]. Additionally, for TCM a demapper needs to be employed that delivers the most likely subset signal at a certain time.…”

Section: Survivor Path Unitmentioning

confidence: 99%

“…Depending on the algorithm used for the SP unit, the architecture becomes more or less related to the number of bits b and states N per trellis stage. For example, the register-exchange algorithm requires the trellis to be directly mapped onto hardware [8], which gives a stronger connection to b and N.…”

Section: Introductionmentioning

confidence: 99%

Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS

Kamuf¹,

Rodrigues²,

Anderson³

et al. 2010

Microprocessors and Microsystems

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This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8 V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.

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“…Nevertheless, the signature-based error detection schemes proposed in [5] can improve the reliability of the decoder circuits with minimum hardware redundancy. The hybrid VLSI architectures for SMU presented in [10] combine the benefits of Register Exchange (RE) and Traceforward (TF) algorithms to improve the latency and storage requirements of the Viterbi Decoder by trading-off implementation efficiency. However, as per the concern in the VLSI hardware implementation, BMU and SMU transpire to be purely forward logic, whereas PMU is recursive.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, PMU becomes an imperative power dissipator and speed bottleneck in achieving high throughput for the Viterbi decoder [11]. PMU also occupies a significant area (dependent on the transistor count) deeming its design [5,10,12]. The Add-Compare-Select (ACS) computational units in the PMU are time shared by several states in low-speed Viterbi Decoders whereas, there are ACSUs (equivalent to the number of states) in the PMU of a high-speed Viterbi Decoder [13].…”

Section: Introductionmentioning

confidence: 99%

Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles

2020

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The Viterbi Algorithm is a recursive optimal solution for estimating the most likely state sequence of discrete-time finite-state Markov process and Hidden Markov Models (HMM) observed in memoryless noise. The Viterbi algorithm is extensively used for decoding convolutional codes, in the constraint length k that encompasses its use in digital communications specifically in satellite and cellular communications. Storage devices to speed up access, speech synthesis and recognition technologies use the Viterbi algorithm or its variants. In this paper low-power, high-speed and reduced transistor count Viterbi decoding circuits with enhanced error detection capabilities are designed and implemented with signature-based error detection schemes in three design logic styles primarily Conventional CMOS, Hybrid logic and GDI. The significance of the work is the upshot of realizing low latency and low power dissipation with high reliability in the iterative process of finding the least path metric by superseding the subtractor in CSA & PCSA circuits with an optimized comparator. When evaluated against the Traditional/Benchmark CSA & PCSA circuits, the Conventional CMOS design approach attains low power consumption and high accuracy with a reduction in average power dissipation by 4.69% and 3.83% and an improvement in delay performance by 7.89% and 3.79% respectively, with a tradeoff for high area utilization. Whereas, the GDI design approach results in an extreme reduction of transistor count by 71.52% and 74.94% with a weaker logic swing for CSA & PCSA units respectively, complimented by an increase in power dissipation (approximately multiplied by a factor of 5) and deterioration in delay performance by one order of magnitude. The Hybrid logic stages CSA & PCSA units that are 32.52% and 9.27% faster and achieve optimization in area utilization by 48.68% and 51.09% respectively, at the expense of elevated power dissipation by one order of magnitude. All the circuits were designed and simulated using GPDK 90 nm technology libraries on Cadence Design Suite 6.1.6 platform at 27°C temperature on 1.2 V supply-rail and SPICE codes were generated as well.

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Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward

Cited by 12 publications

References 10 publications

Power-efficient decoder implementation based on state transparent convolutional codes

Power-efficient decoder implementation based on state transparent convolutional codes

Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS

Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles

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