SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support

Wang, Xiaodong; Chen, Shuang; Setter, Jeff; Martínez, José F.

doi:10.1109/hpca.2017.65

Cited by 45 publications

(25 citation statements)

References 29 publications

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“…However, these works will not be as effective as before on newer architectures (e.g., Haswell and Skylake), as the mapping between LLC slices and physical addresses changes at a finer granularity than 4kpages. Furthermore, there are a series of works that proposed [6,51,75,76] or exploited [17,63,64,[81][82][83] hardware-based cache partitioning to better use the LLC in order to improve performance. To the best of our knowledge, none of these works considered LLC slice-aware memory management, or slice-aware cache partitioning, and we are the only work that takes advantage of knowledge of Intel's LLC Complex Addressing for memory management and allocation.…”

Section: Related Workmentioning

confidence: 99%

Make the Most out of Last Level Cache in Intel Processors

Farshin

Roozbeh

Maguire

et al. 2019

Proceedings of the Fourteenth EuroSys Conference 2019

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In modern (Intel) processors, Last Level Cache (LLC) is divided into multiple slices and an undocumented hashing algorithm (aka Complex Addressing) maps different parts of memory address space among these slices to increase the effective memory bandwidth. After a careful study of Intel's Complex Addressing, we introduce a sliceaware memory management scheme, wherein frequently used data can be accessed faster via the LLC. Using our proposed scheme, we show that a key-value store can potentially improve its average performance ∼12.2% and ∼11.4% for 100% & 95% GET workloads, respectively. Furthermore, we propose CacheDirector, a network I/O solution which extends Direct Data I/O (DDIO) and places the packet's header in the slice of the LLC that is closest to the relevant processing core. We implemented CacheDirector as an extension to DPDK and evaluated our proposed solution for latency-critical applications in Network Function Virtualization (NFV) systems. Evaluation results show that CacheDirector makes packet processing faster by reducing tail latencies (90-99 t h percentiles) by up to 119 µs (∼21.5%) for optimized NFV service chains that are running at 100 Gbps. Finally, we analyze the effectiveness of slice-aware memory management to realize cache isolation.

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Section: Related Workmentioning

confidence: 99%

Make the Most out of Last Level Cache in Intel Processors

Farshin

Roozbeh

Maguire

et al. 2019

Proceedings of the Fourteenth EuroSys Conference 2019

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“…When hyper-threading is disabled, interference harms envy-freeness by 18% instead of 32%. Second, we could deploy new microarchitectures that guarantee isolation for the last-level cache and memory channel [26,45,57,65]. Finally, agents could continuously update their utility profiles and re-optimize their thresholds.…”

Section: Sensitivity To Interferencementioning

confidence: 99%

Managing Heterogeneous Datacenters with Tokens

Zahedi

Fan

Lee

2018

ACM Trans. Archit. Code Optim.

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Ensuring fairness in a system with scarce, preferred resources requires time sharing. We consider a heterogeneous system with a few "big" and many "small" processors. We allocate heterogeneous processors using a novel token mechanism, which frames the allocation problem as a repeated game. At each round, users request big processors and spend a token if their request is granted. We analyze the game and optimize users' strategies to produce an equilibrium. In equilibrium, allocations balance performance and fairness. Our mechanism outperforms classical, fair mechanisms by 1.7×, on average, in performance gains, and is competitive with a performance maximizing mechanism. CCS Concepts: • Software and its engineering → Power management; • Information systems → Data centers; • Social and professional topics → Pricing and resource allocation; • Theory of computation → Algorithmic mechanism design; • Computing methodologies → Modeling methodologies;

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“…The behavior of cache determines system performance due to its ability to bridge the speed gap between the processor and main memory. To tolerate the memory access latency, there have been a plethora of proposals for data prefetching [2][3][4][5][6][7][8][9][10]. Data prefetching techniques improve performance by predicting future memory accesses and fetch them in cache before they are accessed.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, with the advent of chip multiprocessors (CMP) architectures, thread-based prefetching and speculative execution techniques have received much attention in the research community [2,6,9]. One novel method, called helper threaded prefetching, utilizes a helper thread to boost the performance of the main thread by prefetching data into cache.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvements by Deploying L2 Prefetchers with Helper Thread for Pointer-Chasing Applications

Huang¹

2018

IJPE

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Modern processor micro-architecture offers advanced prefetch mechanisms that are designed to effectively hide memory latency and improve application performance. However, pointer-chasing applications employing linked data structures expose a memory latency problem that is difficult to deal with by using hardware prefetchers. It is promising that helper threaded prefetching based on Chip Multiprocessor is an effective method for reducing the memory latency of accesses to linked data structures. In this paper, we first illustrated two L2 prefetchers on Chip Multiprocessor and two different helper threaded prefetching techniques for pointer-chasing applications. Then, we revealed the limitations of L2 prefetchers for pointer-intensive applications after applying two different threaded prefetching techniques. Finally, we optimized the deployment of L2 prefetchers with two different threaded prefetching techniques for pointer-chasing applications. The experimental results indicate that L2 prefetchers' effectiveness on helper threads depends on the memory access pattern of the targeted applications, and the optimized deployment of L2 prefetchers further improves the performance of pointer-intensive applications.

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SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support

Cited by 45 publications

References 29 publications

Make the Most out of Last Level Cache in Intel Processors

Make the Most out of Last Level Cache in Intel Processors

Managing Heterogeneous Datacenters with Tokens

Performance Improvements by Deploying L2 Prefetchers with Helper Thread for Pointer-Chasing Applications

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