Switch level hot-carrier reliability enhancement of VLSI circuits

Abstract

Long-term reliability of MOS VLSI circuits is becoming an important issue with rapid advances in VLSI technology and increasing VLSI chip densities. Hot-carrier effects and electromigration are the two important failure mechanisms that significantly impact the long-term reliability of high-density VLSI ICs. In this paper, we present a probabilistic switch-level method for identifying MOSFETs in the circuit that are most susceptible to hot-carrier effects. Subsequently, we outline two techniques -(i) reordering of inputs to logic gates and (SI selective MOSFET sizing -to reduce the hot-carrier susceptibility of these critical MOSFETs. Finally, we show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption. The algorithms are incorporated into SIS and are evaluated on the ISCAS-MCNC91 benchmark suite.

Investigating Simple Low Latency Reliable Multiported Register Files

“…Over time the use of the transistors changes their properties with the expectation that hot carrier effects and negative bias temperature instability will become a concern for lifetime reliability of transistors in general and SRAMs in particular [17,18]. Stuck at, stuck open, or stuck short faults are another source of hard errors [19].…”