Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)
DOI: 10.1109/iccdcs.2000.869819
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Switching noise due to internal gates: delay implications and modeling

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Cited by 4 publications
(5 citation statements)
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“…The parabolic relation between the number of switching gates and noise peak is obvious due to negative feedback effect. In the meantime, the Gomez's method [4] agrees with the SPICE simulation only when the ground bounce is small. As the number of switching gates increases, Gomez's method introduces errors due to neglecting the impact of the internal power rail and the peak shift.…”
Section: Analysis and Discussionsupporting
confidence: 50%
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“…The parabolic relation between the number of switching gates and noise peak is obvious due to negative feedback effect. In the meantime, the Gomez's method [4] agrees with the SPICE simulation only when the ground bounce is small. As the number of switching gates increases, Gomez's method introduces errors due to neglecting the impact of the internal power rail and the peak shift.…”
Section: Analysis and Discussionsupporting
confidence: 50%
“…However, if the SSN due to internal gate switching is considered, this method is invalid because the signal bounce in power rail is not negligible [2]. Consider the circuit shown in Figure 2 [4], where LC pin models are used for both power rail and ground rail, C Ln (C Lp ) includes the load capacitance of fan-outs and wire capacitance. The equivalent gate-to-drain capacitance C ff is the sum of C gd from both nMOS and pMOS transistors.…”
Section: Lumped Model Analysismentioning
confidence: 99%
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