“… The 64 CPE independently obtained data for calculation at the same time, and the starting position of each CPE to obtain data was coreindex, which was calculated according to the slave core number (_PEN) and the number of row-slices in the task block (lsn). The specific calculation method is shown in formula (5).…”
Section: Data Storage Transformation Strategymentioning
confidence: 99%
“…Each CPE has an independent instruction cache and 256KB local data memory (LDM) that is consisted of SPM. The LDM of CPE is identical to a cache that can improve data access speed 4,5 .…”
The irregular distribution of non-zero elements of large-scale sparse matrix leads to low data access efficiency caused by the unique architecture of the Sunway many-core processor, which brings great challenges to the efficient implementation of sparse matrix-vector multiplication (SpMV) computing by SW26010P many-core processor. To address this problem, a study of SpMV optimization strategies is carried out based on the SW26010P many-core processor. Firstly, we design a memorized data storage transformation strategy to transform the matrix in CSR storage format into BCSR storage. Secondly, the dynamic task scheduling method is introduced to the algorithm to realize the load balance between slave cores. Thirdly, the LDM memory is refined and designed, and the slave core dual cache strategy is optimized to further improve the performance. Finally, we selected a large number of representative sparse matrices from the Matrix Market for testing. The results show that the scheme has obviously speedup the processing procedure of sparse matrices with various sizes and sizes, and the master-slave speedup ratio can reach up to 38 times. The optimization method used in this paper has implications for other complex applications of the SW26010P many-core processor.
“… The 64 CPE independently obtained data for calculation at the same time, and the starting position of each CPE to obtain data was coreindex, which was calculated according to the slave core number (_PEN) and the number of row-slices in the task block (lsn). The specific calculation method is shown in formula (5).…”
Section: Data Storage Transformation Strategymentioning
confidence: 99%
“…Each CPE has an independent instruction cache and 256KB local data memory (LDM) that is consisted of SPM. The LDM of CPE is identical to a cache that can improve data access speed 4,5 .…”
The irregular distribution of non-zero elements of large-scale sparse matrix leads to low data access efficiency caused by the unique architecture of the Sunway many-core processor, which brings great challenges to the efficient implementation of sparse matrix-vector multiplication (SpMV) computing by SW26010P many-core processor. To address this problem, a study of SpMV optimization strategies is carried out based on the SW26010P many-core processor. Firstly, we design a memorized data storage transformation strategy to transform the matrix in CSR storage format into BCSR storage. Secondly, the dynamic task scheduling method is introduced to the algorithm to realize the load balance between slave cores. Thirdly, the LDM memory is refined and designed, and the slave core dual cache strategy is optimized to further improve the performance. Finally, we selected a large number of representative sparse matrices from the Matrix Market for testing. The results show that the scheme has obviously speedup the processing procedure of sparse matrices with various sizes and sizes, and the master-slave speedup ratio can reach up to 38 times. The optimization method used in this paper has implications for other complex applications of the SW26010P many-core processor.
“…Each CPE has an independent instruction cache and 256 KB local data memory (LDM) that is consisted of SPM. The LDM of CPE is identical to a cache that can improve data access speed 4 , 5 . Figure 1 General architecture of the SW26010P many-core processor.…”
The irregular distribution of non-zero elements of large-scale sparse matrix leads to low data access efficiency caused by the unique architecture of the Sunway many-core processor, which brings great challenges to the efficient implementation of sparse matrix–vector multiplication (SpMV) computing by SW26010P many-core processor. To address this problem, a study of SpMV optimization strategies is carried out based on the SW26010P many-core processor. Firstly, we design a memorized data storage transformation strategy to transform the matrix in CSR storage format into BCSR (Block Compressed Sparse Row) storage. Secondly, the dynamic task scheduling method is introduced to the algorithm to realize the load balance between slave cores. Thirdly, the LDM memory is refined and designed, and the slave core dual cache strategy is optimized to further improve the performance. Finally, we selected a large number of representative sparse matrices from the Matrix Market for testing. The results show that the scheme has obviously speedup the processing procedure of sparse matrices with various sizes and sizes, and the master–slave speedup ratio can reach up to 38 times. The optimization method used in this paper has implications for other complex applications of the SW26010P many-core processor.
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