Symbiotic organisms search algorithm for optimal design of CMOS two‐stage op‐amp with nulling resistor and robust bias circuit

Ghosh, Sumalya; De, Bishnu Prasad; Kar, Rajib; Mal, Ashis Kumar

doi:10.1049/iet-cds.2018.5259

Cited by 14 publications

(9 citation statements)

References 27 publications

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“…Therefore, many optimization schemes for analog circuit design have been reported by many researchers. The most well-known techniques are g m /I D methodology [36,37], mathematical heuristics such as Particle Swarm Optimization (PSO) [38], Ant Colony Optimization (ACO) [39], Genetic Algorithms (GA) [40], and Symbiotic Organisms Search Algorithm [41]. The g m / I D methodology is a popular one used for sizing low power and low noise analog building blocks using a simulationbased datasheet of transistors.…”

Section: Noise Analysismentioning

confidence: 99%

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An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

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An efficient architecture of a high-performance ultra-low-voltage gate-driven two-stage pseudo-fully differential operational transconductance amplifier (OTA) is presented. The proposed subthreshold-region operated OTA utilizes two identical conventional current-mirror-based source coupled pseudo-differential amplifiers with their cross-connected gate as core amplifier blocks. The input core differential pair exploiting forward body terminal biasing scheme at output load employed in cascaded stages essentially improves the overall transconductance more than twice compared to the conventional pseudo-differential pair based OTA and achieves near rail-to-rail output voltage swing (90.2% of supply voltage) for near rail-to-rail input common-mode voltage (94.92% of supply voltage). The circuit is designed and optimized using g m /I D technique associated with the Particle Swarm Optimization (PSO) algorithm with a single supply of 0.35 V for a capacitive load of 10 pF and simulated in Cadence Virtuoso analog environment using UMC 180-nm CMOS technology. Post-layout simulations have been accomplished to justify the performance of the proposed OTA. It achieves an open-loop gain of 83.00 dB, phase margin of 61.48°, and power dissipation of 35.04 nW at a unity gain frequency of 24.78 kHz. A low-frequency continuous second-order G m -C filter is also implemented to validate its workability. Simulation results of this work are compared to the state-of-the-art architecture available, and enhanced performance is validated. Keywords Operational transconductance amplifier (OTA) Á Unity gain frequency (UGF) Á Subthreshold region Á Input common-mode range (ICMR) Á Biquad G m -C filter & Sougata Ghosh

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Section: Noise Analysismentioning

confidence: 99%

“…The DC gain or passband gain (A P ) and corner or cut-off frequency (f C ) of the filter is determined from Eqs. (41,42) and Eqs. (42, 44), respectively, are given by…”

Section: G M -C Filter Designmentioning

confidence: 99%

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

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“…Equation-based and simulation-based approaches are two of the most commonly used ways for design automation of complementary metal-oxidesemiconductors (CMOS) analog circuits, where the design equations and simulator are employed in the synthesis stage of circuit design, respectively. The stateof-the-art literature shows that metaheuristic algorithms such as particle swarm optimization (PSO) [1][2][3][4][5][6], greywolf optimization (GWO) [7,8] algorithm, enhanced version of GWO (EGWO) algorithm [9], whale optimization algorithm (WOA) [10][11][12], symbiotic organisms search algorithm [13], ALC-PSO algorithm [14,15] and a hybrid of WOA, and modified GWO (mGWO) algorithms (WOA-mGWO) [16] have been successfully applied and are used for the optimal design of various CMOS analog and radio frequency circuits using various design equations that help in developing the cost function and design constraints [17]. Similarly, different optimization algorithms are used for enhanced optimization of analog ICs using simulated results instead of derived results, such as hierarchical PSO (HPSO) [18] and PSO [19], a clustered gravitational search algorithm [20], GSA, advanced GSA (AGSA), and advanced GSA-PSO algorithms [21,22].…”

Section: Introductionmentioning

confidence: 99%

Machine learning‐based design automation of CMOS analog circuits using SCA‐mGWO algorithm

Syamala²

2022

ETRI Journal

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Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified greywolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

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“…Referring to the existing literatures, the optimal design of the transistor size using the intelligent optimization, such as the craziness-based particle swarm optimization algorithm (SOA), genetic algorithm (GA) and ant colony optimization (ACO) algorithm has been implemented to some analogue circuits, for example, operational amplifier, operational trans-conductance amplifier, and differential amplifiers etc. [9][10][11][12][13][14][15]. Moreover, by introducing proper cost function, the optimal design process can satisfy all of the design constraints and multiple optimization objectives.…”

Section: Introductionmentioning

confidence: 99%

Optimal design of 10‐bit single‐slope ADC for CMOS image sensor based on swarm intelligent optimization algorithm

Zhu

et al. 2021

IET Circuits, Devices & Syst

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As one of the most critical blocks of the CMOS image sensor (CIS), the accuracy and power consumption of the analogue-to-digital converter (ADC) play an important role in its performance. However, due to the mutually restrictive relationship between power consumption and accuracy in the single-slope ADC (SS ADC), it is difficult to improve these performance indexes meantime without an efficient optimal design method. Here, an optimal design methodology based on an improved artificial fish swarm optimization algorithm (IAFSOA) is proposed for a 10-bit SS ADC in CIS. First, a voltage storage structure and offset calibration circuit are developed for promoting the performance of the comparator. Then, IAFSOA is developed for the circuit parameters optimization with faster convergence rate and higher computational accuracy. The proposed multiobjectives optimization algorithm can obtain the optimal parameters of the kernel circuit components and lead to an enhancement of both power consumption and accuracy. The optimized SS ADC is designed based on 0.18 µm process to verify the effectiveness of the proposed method. Compared to the earlier reported work, the IAFSOA-based optimal design method can promote the performance of the SS ADC by an improvement of effective number of bits and a reduction of power consumption.This is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Symbiotic organisms search algorithm for optimal design of CMOS two‐stage op‐amp with nulling resistor and robust bias circuit

Cited by 14 publications

References 27 publications

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Machine learning‐based design automation of CMOS analog circuits using SCA‐mGWO algorithm

Optimal design of 10‐bit single‐slope ADC for CMOS image sensor based on swarm intelligent optimization algorithm

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