This study suggests an evolutionary technique namely symbiotic organisms search (SOS) algorithm based optimal designs of two different analogue very-large-scale integration circuits. The configurations considered here are nulling resistor compensation based complementary metal-oxide-semiconductor (CMOS) two-stage op-amp and two-stage CMOS op-amp with robust bias circuit. The prime goal of this work is the sizing of metal-oxide-semiconductor (MOS) transistors employing the SOS algorithm to optimise the area occupied by the individual circuit. Design results based on the SOS algorithm are authenticated with SPICE simulation. SPICE simulation results reveal that all the design specifications are firmly satisfied for both the circuits. Moreover, SPICE based results show that the SOS algorithm provides much better results compared to the earlier reported techniques regarding the gain, MOS area and power dissipation for the abovementioned op-amp circuits.

In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.

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In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[Formula: see text]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The designed LNA shows a gain of 15.28[Formula: see text]dB, NF of 0.376[Formula: see text]dB, the power dissipation of 936[Formula: see text][Formula: see text]W and IIP3 of [Formula: see text][Formula: see text]dBm at 2.4[Formula: see text]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[Formula: see text]mW[Formula: see text] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.