Symbolic hazard-free minimization and encoding of asynchronous finite state machines

Abstract

-This paper presents an automated method for the synthesis of multiple-input-change (MIC) asynchronous state machines. Asynchronous state machine design is subtle since, unlike synchronous synthesis, logic must be implemented without hazards, and state codes must be chosen carefully to avoid critical races. We formulate and solve an optimal hazard-free and critical race-free encoding problem for a class of MIC asynchronous state machines called burst-mode. Analogous to a paradigm successfully used for the optimal encoding of synchronous machines, the problem is formulated as an input encoding problem. Implementations are targeted to sum-of-product realizations. We believe this is the first general method for the optimal encoding of hazard-free MIC asynchronous state machines under a generalized fundamental mode of operation. Results indicate that improved solutions are produced, ranging up to 17% improvement. INTRODUCTIONThere has been a renewed interest in asynchronous design, because of their potential for high-performance, modularity and avoidance of clock skew. This paper focuses on one class of asynchronous designs: asynchronous state machines.Several methods have recently been introduced for the synthesis of asynchronous state machines [9,17,8]. These methods have been automated and produce low-latency machines which are guaranteed hazard-free at the gate-level. The design tools have benefited from a number of hazard-free optimization algorithms: exact two-level logic minimization [10], multi-level logic optimization [15,3,4], and technology mapping [13]. However, none of these methods includes algorithms for optimal state assignment. The contribution of this paper is a general method for the optimal state assignment of asynchronous state machines.Optimal state assignment of synchronous machines has been an active area of research. De Micheli [7] formulated and solved an input encoding problem, which approximates an optimal state assignment for PLA-based state machines. Other formulations as an output encoding or input/output encoding problem have also been developed [6,16,12,1].Synchronous state assignment methods are inadequate for asynchronous designs, since the resulting machines may have critical races and logic hazards. In this paper, we consider two related problems in the synthesis of asynchronousstate machines: critical race-free state encoding and hazard-free logic minimization. In existing synthesis trajectories [17,8], these problems are solved separately, where state assignment is typically performed without regard to the optimality of the eventual logic implementation,

Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity

“…The MINIMALIST tool [7], [8] is a design package for BM controller automatic synthesis. The tool provides two-level low-latency implementations using standard cells, while guaranteeing hazard-freedom, i.e., absence of glitches both internally and at the controllers' interfaces.…”

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

“…A number of optimization algorithms and CAD tools have been developed, for sequential and combinational logic synthesis [23,53,66,36,39], technology mapping [61], timing analysis [10], and synthesis for testability [54]. Burstmode CAD tools have been applied to several industrial designs, including an experimental routing chip [17] and low-power infrared communications chip [40] at HP Laboratories, an experimental SCSI controller at AMD [81], and a high-performance experimental instruction-length decoder at Intel [60].…”

State encoding of large asynchronous controllers

“…In the area of asynchronous controllers, the methods proposed for Burst-mode (BM) machines [8] and Signal Transition Graphs (STGs) [4], among others, are the ones that have had the most relevant impact.…”