Symmetric Cascaded H-Bridge Multilevel Inverter With Enhanced Multi-Phase Fault Tolerant Capability

Neyshabouri, Yousef; Monfared, Kourosh Khalaj; Iman‐Eini, Hossein; Farhadi‐Kangarlu, Mohammad

doi:10.1109/tie.2021.3114745

Cited by 22 publications

(5 citation statements)

References 33 publications

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“…Each of these losses is estimated separately using different equations. Conduction loss can be calculated using equation ( 6), switching loss can be calculated using equation (7), and diode conduction loss can be calculated using equation (8). The total loss of the converter can be calculated using equation (9).…”

Section: A Conventional Methodsmentioning

confidence: 99%

“…number of conduction devices, capacitor voltage balance, and a problem with system shutdown in the event of source, switch, or capacitor failure. In light of this, current research in the MLI sector has been on building novel topologies with a decreased number of devices [4], fault tolerance features [5], [6], [7], [8], and intrinsic capacitor voltage balancing [9]. In order to create an MLI topology with a smaller number of devices, IRPs must be sacrificed, but fault-tolerant qualities and intrinsic capacitor voltage balancing may be satisfied most effectively if the latter exists largely.…”

Section: Introductionmentioning

confidence: 99%

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Techniques to Reduce Capacitor Voltage Ripples in Multilevel Inverters

Gautam,

Jalhotra,

Iqbal

et al. 2023

IEEE Access

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Reducing ripples on the capacitor voltage has two benefits: improved output waveform quality and accurate converter size. During the generation of a given output voltage level, the factor ''Inherent Redundant Paths (IRPs)'' has a considerable impact on the characteristics of multilevel inverter design. The consistent distribution of power loss derives from the Active Neutral Point-Clamed Inverter's intrinsic redundant route at zero-voltage level generation. Even though it has been claimed that adding intrinsically redundant routes might give fault-tolerance capabilities to MLI topologies, the utilization of these pathways at intermediate voltage levels has not yet been studied. Based on this, the current research provides a unique charging and discharging technique is known as the alternating charging and discharging approach, which reduces capacitor voltage ripple. In addition, the suggested technique permits the inherent voltage balancing of capacitors without the need for supplemental components. The suggested alternative charging and discharging approach is implemented under both healthy and varied switch failure circumstances. In a laboratory prototype, the efficacy of the suggested alternative charging and discharging technique has been empirically tested.INDEX TERMS Capacitor voltage ripple reduction, inherent redundant paths, multilevel inverters, uniform power losses. the Ph.D. degree (Hons.

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Section: A Conventional Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Techniques to Reduce Capacitor Voltage Ripples in Multilevel Inverters

Gautam,

Jalhotra,

Iqbal

et al. 2023

IEEE Access

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show abstract

“…The most prominent MLI has been categorized into three parts: Cascaded H-bridge (CHB), Flying capacitor (FC) and Neutral Point Clamped (NPC) MLI [9]. Because of its modular structure, CHB MLI nds a wide range of applications as compared to the other topologies [10], but the number of components used is high. To reduce the number of components PUC MLI is proposed [11][12] [13].…”

Section: Introductionmentioning

confidence: 99%

“…MLI generally suffers from open circuit (OC) and short circuit (SC) faults across the power electronics switches [19]. A switch failure might harm the MLI healthy components in addition to impairing its usual function [10]. SC fault happens as a result of aberrant fault current.…”

Section: Introductionmentioning

confidence: 99%

Multiple Fault Tolerant PUC Multilevel Inverter Using the Concept of Redundancy with Low Total Blocking Voltage, Device Count and High Post-Fault Efficiency for Five Switches Fault

Phukan,

Tiwari,

Singh

et al. 2024

Preprint

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In this article, a fault-tolerant Packed U Cell MLI (FT-PUC-MLI) is presented, which utilizes two DC sources with nine main switches and eight redundant switches for creating 7-level across the output. The proposed topology uses phase disposition sinusoidal pulse width modulation (PD-SPWM) for the generation of gate signals. A detailed analysis of the proposed topology is done with respect to efficiency, power loss and total harmonics distortions (THD). A brief comparative analysis in terms of device count, total blocking voltage, post and pre fault efficiency, post and pre fault voltage levels is being done. The proposed topology can tolerate single-switch and multiple-switch failures, thus enabling it to be used for emergency loads. The proposed topology maintains a constant output voltage level in the post-fault period. The simulation of FT-PUC-MLI topology is carried out by using the MATLAB/SIMULINK platform with all possible switch fault combinations and real time simulation is also being done in OPAL RT 4510.

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“…Some of the papers made use of the switching redundancy [17], others used DC-Bus midpoint connection [18], other researcher added redundant switches or leg [19][20][21]. Finally, different techniques were used in literature to maintain the operation of the multi-level inverter including neutralshift, DC-bus voltage reconfiguration, and redundant modules installation is employed [22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Sensorless Control of a PMSM Drive Post an Open Circuit Failure Based on 3D‐SVPWM Technique

Saleh

Sumner

2022

IEEJ Transactions Elec Engng

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This paper presents a novel technique to maintain the PMSM Drive operation post the failure in one phase and the failure of the speed sensor occur simultaneously. The PMSM motor is driven by a fault-tolerant inverter. The use of the fault-tolerant inverter associated with the using of the 3-Dimension space vector pulse width modulation (3-D SVPWM) allow the PMSM drive to maintain its performance post the failure in one phase. Moreover, the stability of the PMSM drive system is furtherly enhanced through utilizing a novel algorithm to obtain the rotor position and speed post the failure in the speed sensor. The algorithm is based on measuring the transient response of the remaining healthy currents post the failure due to the inverter switching actions. The results that are obtained through simulation prove the reliability of the system to maintain its operation post the failure in one phase of the motor and the failure in the speed sensor occurred simultaneously. Also, the results demonstrate the effectiveness of the proposed technique to maintain the performance of the PMSM drive system under different speeds steps and load conditions post the failure.

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Symmetric Cascaded H-Bridge Multilevel Inverter With Enhanced Multi-Phase Fault Tolerant Capability

Cited by 22 publications

References 33 publications

Techniques to Reduce Capacitor Voltage Ripples in Multilevel Inverters

Techniques to Reduce Capacitor Voltage Ripples in Multilevel Inverters

Multiple Fault Tolerant PUC Multilevel Inverter Using the Concept of Redundancy with Low Total Blocking Voltage, Device Count and High Post-Fault Efficiency for Five Switches Fault

Sensorless Control of a PMSM Drive Post an Open Circuit Failure Based on 3D‐SVPWM Technique

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