Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

“…[1][2][3][4][5][6] Compared with amorphous silicon TFTs, LTPS TFTs have demonstrated higher mobility, [7][8][9] which could be further improved by adopting advanced fabrication techniques such as the use of a high-k material, patterning, and various structures. [10][11][12][13][14][15][16][17][18] However, as TFTs have been scaled down, the adverse effects of the inherent grain boundary (GB) on electrical characteristics and their reliability have become significant. [19][20][21][22] To mitigate GB effects in polycrystalline silicon (poly-Si) channel TFTs, several methods such as plasma treatment, control of grain growth direction, and adjustment of GB location in poly-Si channels have been proposed.…”

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

“…Self-aligned dual-gate polycrystalline-Si (poly-Si) TFTs are known to be promising for TFT technology because of their advantages of low leakage current, low parasitic capacitance, and high mobility [15][16][17]. Wu et al fabricated a selfaligned dual-gate poly-Si TFT using a metal-induced lateralcrystallization method [16].…”

“…Wu et al fabricated a selfaligned dual-gate poly-Si TFT using a metal-induced lateralcrystallization method [16]. A vertical-channel Ni-salicided TFT fabricated based on a self-aligned dual-gate poly-Si TFT was proposed in [15]. Yeh et al employed self-aligned mutigate poly-Si field-effect transistors to fabricate a nonvolatile memory [17].…”