Symmetrical unified compact model of short-channel double-gate MOSFETs

Papathanasiou, K.; Theodorou, Christoforos; Tsormpatzoglou, A.; Tassis, D. H.; Dimitriadis, C. A.; Bucher, Matthias; Ghibaudo, G.

doi:10.1016/j.sse.2011.10.002

Cited by 20 publications

(10 citation statements)

References 22 publications

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“…Expression (5) is the result of the unification of the drain current equations in the weak and strong inversion regions in the case of DG FinFETs, which is valid in all regions of operation [20].…”

Section: A Gate Chargementioning

confidence: 99%

See 1 more Smart Citation

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Fasarakis

Tsormpatzoglou

Tassis

et al. 2012

IEEE Trans. Electron Devices

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A charge-based compact capacitance model has been developed describing the capacitance-voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward-Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source transcapacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers.

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Section: A Gate Chargementioning

confidence: 99%

“…using the unified inversion sheet charge density q i valid in all regions of operation [18], [20], i.e.,…”

Section: A Gate Chargementioning

confidence: 99%

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Fasarakis

Tsormpatzoglou

Tassis

et al. 2012

IEEE Trans. Electron Devices

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“…The proposed ϕ model is also verified with the industry standard professional device simulator (Silvaco -ATLAS). Addition to this, the ds I model is proposed from the existing models for symmetrical n-channel DG MOSFET [21][22][23][24] considering drift-diffusion approach. The reported ds I model is improved by incorporating physical effects like threshold voltage roll-off, channel length modulation and surface roughness scattering.…”

Section: Introductionmentioning

confidence: 99%

“…In order to smoothen the , ds long I model Eq. (22) in the transition from subthreshold to linear region of operation, a flag called isSI [24] has been used.…”

Section: Introductionmentioning

confidence: 99%

Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation

Ahmed

Saha

2019

Period. Polytech. Elec. Eng. Comp. Sci.

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In the present era, down scaling of complementary metal-oxide-semiconductor (CMOS) technology has lead the metal-oxide-semiconductor field-effect-transistor's (MOSFET) sizes to nanometer regime which in turn experiencing difficulties due to the effect of physical and technological perspective. Double-gate (DG) MOSFET is considered as a promising device to reduce the shortcoming and shrink down towards nanometer domain. This paper proposes electrostatic potential distribution and drain current models for the lightly doped symmetrical p-channel DG MOSFET. The analytic solution of potential distribution is derived by solving the 2D Poisson's equation incorporated with hole density through the superposition method. The drain current model has been explored by incorporating physical effects like threshold-voltage roll-off, channel length modulation and surface roughness scattering. Functionality of the models has been calculated in MATLAB and the obtained results are verified and compared with state of the art literature.

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“…Significant research are performed on compact modelling of different multiple gate structures. Among those, symmetric or asymmetric DGFET structure has been extensively studied [14][15][16][17][18][19][20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

2D Surface potential and mobility modelling of doped/undoped symmetric double gate MOSFET

Bose

Roy

2019

IET Circuits, Devices & Systems

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The 2D surface potential and mobility models are proposed for symmetric doped/undoped channel double gate FET (DGFET) device. This is then used in drain current equation obtained by combining Pao-Sah's double integral formula with Pierret-Shields' type current model. The surface potential model and mobility model both are analytic and differently solved for both undoped and doped device. Being an explicit and continuous expression, the drain current model is used to describe the behaviour of the device at below and above threshold condition. Simulations are carried out using TCAD Sentaurus bundle of Synopsis tool. The accuracy of the proposed model is analysed and compared with the simulation result for different channel length and channel thickness value of the device.

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Symmetrical unified compact model of short-channel double-gate MOSFETs

Cited by 20 publications

References 22 publications

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation

2D Surface potential and mobility modelling of doped/undoped symmetric double gate MOSFET

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