Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Abstract

-The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits

“…Devices mismatch can be attributed to two sources of errors: random mismatch and systematic mismatch [Liu et al 2008]. Random mismatch is usually caused by process Authors' addresses: C.-C. Huang (corresponding author) and J.-E. Chen, Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, Taiwan; C.-L. Wey, Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan; P.-W. Luo, Industrial Technology Research Institute, Hsinchu, Taiwan; corresponding author's email: lynden.huang@gmail.com.…”