Synaptic Control for Hardware Implementation of Spike Timing Dependent Plasticity

Abstract

Spiking neural networks (SNN) are biologically plausible networks. Compared to formal neural networks, they come with huge benefits related to their asynchronous processing and massively parallel architecture. Recent developments in neuromorphics aim to implement these SNNs in hardware to fully exploit their potential in terms of low energy consumption. In this paper, the plasticity of a multi-state conductance synapse in SNN is shown. The synapse is a compound of multiple Magnetic Tunnel Junction (MTJ) devices connected in parallel. The network performs learning by potentiation and depression of the synapses. In this paper we show how these two mechanisms can be obtained in hardware-implemented SNNs. We present a methodology to achieve the Spike Timing Dependent Plasticity (STDP) learning rule in hardware by carefully engineering the post-and pre-synaptic signals. We demonstrate synaptic plasticity as a function of the relative spiking time of input and output neurons only.

Bi-sigmoid spike-timing dependent plasticity learning rule for magnetic tunnel junction-based SNN

“…Our work addresses this gap by introducing a hardware implementation of STDP with clear time dependence which is suitable for SNNs. We demonstrate the careful selection of signal shapes to emulate pre- and post-synaptic spikes, enabling the implementation of STDP in hardware (Daddinounou and Vatajelu, 2022 ). In their study, Li et al ( 2014 ) focused on the device level and designed voltage pulse schemes, using different voltage shapes to achieve STDP in chalcogenide memristors, by leveraging the gradual resistance of the synaptic memristor in the microseconds range.…”

Multistate Compound Magnetic Tunnel Junction Synapses for Digital Recognition

“…20,24−33 On the other hand, the design of a compound synapse comprising a parallel array of MTJs on a shared SOT write channel has not been realized until date. 34 reduced number of dedicated transistors for individual bit readout and write operations in the artificial neural network (ANN).…”

“…Early works have shown the potential of binary states (P/AP) MTJs as artificial synapsesfunctional junctions between neuronsin emulating short-term plasticity and long-term potentiation for learning and cognition processes. , Furthermore, artificial synapses endowed with multistate (>2) digital or analog functionalities are posited to be more energy-efficient with enhanced learning accuracy and data acquaintance. − Multistate or analog artificial synapse concepts built upon spatially varied arrangements of MTJs, e.g., in series, and domain wall racetracks, have been explored, albeit with weakly differentiated TMR (<5%) between states, unreliable read-write arising from their inherent thermal instability, and incompatibility with existing CMOS architectures. ,− On the other hand, the design of a compound synapse comprising a parallel array of MTJs on a shared SOT write channel has not been realized until date . Such a design potentially offers well-defined independent states and a reduced number of dedicated transistors for individual bit readout and write operations in the artificial neural network (ANN).…”