Synchronization, coherence, and event ordering in multiprocessors

Dubois, Michel; Scheurich, C.; Briggs, Fayé A.

doi:10.1109/2.15

Cited by 173 publications

(52 citation statements)

References 12 publications

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“…Permitting this indeterminacy improves the performance of the system (e.g., one process can be executed while another waits for data to be input) but can cause problems when the processes must share data or resources. System designers must therefore provide mechanisms that restrict the possible orderings of the instructions by synchronizing the processes (that is, ensuring that particular instructions from different streams are executed at the same time) (Dubois, et al, 1988).…”

Section: Managing Simultaneity Constraintsmentioning

confidence: 99%

The interdisciplinary study of coordination

1994

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This survey characterizes an emerging research area, sometimes called coordination theory , that focuses on the interdisciplinary study of coordination. Research in this area uses and extends ideas about coordination from disciplines such as computer science, organization theory, operations research, economics, linguistics, and psychology. A key insight of the framework presented here is that coordination can be seen as the process of managing dependencies among activities. Further progress, therefore, should be possible by characterizing different kinds of dependencies and identifying the coordination processes that can be used to manage them. A variety of processes are analyzed from this perspective, and commonalities across disciplines are identified. Processes analyzed include those for managing shared resources, producer/consumer relationships, simultaneity constraints , and task/subtask dependencies . Section 3 summarizes ways of applying a coordination perspective in three different domains:(1) understanding the effects of information technology on human organizations and markets, (2) designing cooperative work tools, and (3) designing distributed and parallel computer systems. In the final section, elements of a research agenda in this new area are briefly outlined.

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Section: Managing Simultaneity Constraintsmentioning

confidence: 99%

The interdisciplinary study of coordination

1994

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“…In multicast traffic, a source port simultaneously sends the same cell to many destination ports. Synchronization traffic occurs in distributed applications 19 where a software program is partitioned into a set of cooperating processes that run concurrently on different processors and communicate using message-passing over the interconnection network. Unless properly handled, synchronization traffic can lead to "hot-spot" network congestion 20 as described in the following example.…”

Section: Application Requirementsmentioning

confidence: 99%

OMRAM and ODSP Smart Pixel Chipset Development

Kiamilev¹

2001

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“…The first emulator that we have developed is a system with hardware-enforced cache-coherence under strong or weak ordering of memory accesses [6]. The protocol is directory-based and each memory block has a home node where a directory records the presence and state of copies in every cache [11] [14].…”

Section: Emulation Of Cc-numas With Central Directory Protocolmentioning

confidence: 99%

“…If the store misses in the first-level cache no block is allocated (no allocation on store misses). Under strong ordering of memory accesses [6] (enforcing sequential consistency), the first-level cache and the processor block on each write access which misses or which requires coherence activity in the second-level cache. Under weak ordering of memory accesses there can be a write buffer between the first-and second-level caches (first-level write buffer) and between the second-level cache and the internal bus (second-level write buffer).…”

Section: Emulation Of Cc-numas With Central Directory Protocolmentioning

confidence: 99%

“…A received message is put into a local buffer, which is accessed by the processor when it executes a receive. In the shared-memory model, processors communicate through load and store instructions and some form of explicit synchronization among processors is required at times to avoid data access races [6]. The shared-memory model facilitates fine grain (word level) communication but requires a large number of instructions to transmit large chunks of data, whereas the message-passing model can transmit large amounts of data in a single message.…”

Section: Introductionmentioning

confidence: 99%

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RPM: a rapid prototyping engine for multiprocessor systems

et al. 1995

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In multiprocessor systems, processing nodes contain a processor, some cache and a share of the system memory, and are connected through a scalable interconnect. The system memory partitions may be shared (shared-memory systems) or disjoint (messagepassing systems). Within each class of systems many architectural variations are possible. Fair comparisons among systems are difficult because of the lack of a common hardware platform to implement the different architectures.RPM (Rapid Prototyping engine for Multiprocessors) is a hardware emulator for the rapid prototyping of various multiprocessor architectures. In RPM, the hardware of the target machine is emulated by reprogrammable controllers implemented with Field-Programmable Gate Arrays (FPGAs). The processors, memories and interconnect are off-theshelf and their relative speeds can be modified to emulate various component technologies. Every emulation is an actual incarnation of the target machine and therefore software written for the target machine can be easily ported on it with little modification and without instrumentation of the code.In this paper, we describe the architecture of RPM, its performance and the prototyping methodology. We also compare our approach with simulation and breadboard prototyping.

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Synchronization, coherence, and event ordering in multiprocessors

Cited by 173 publications

References 12 publications

The interdisciplinary study of coordination

The interdisciplinary study of coordination

OMRAM and ODSP Smart Pixel Chipset Development

RPM: a rapid prototyping engine for multiprocessor systems

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