RPM: a rapid prototyping engine for multiprocessor systems

Abstract

In multiprocessor systems, processing nodes contain a processor, some cache and a share of the system memory, and are connected through a scalable interconnect. The system memory partitions may be shared (shared-memory systems) or disjoint (messagepassing systems). Within each class of systems many architectural variations are possible. Fair comparisons among systems are difficult because of the lack of a common hardware platform to implement the different architectures.RPM (Rapid Prototyping engine for Multiprocessors) is a hardware emulator for the rapid prototyping of various multiprocessor architectures. In RPM, the hardware of the target machine is emulated by reprogrammable controllers implemented with Field-Programmable Gate Arrays (FPGAs). The processors, memories and interconnect are off-theshelf and their relative speeds can be modified to emulate various component technologies. Every emulation is an actual incarnation of the target machine and therefore software written for the target machine can be easily ported on it with little modification and without instrumentation of the code.In this paper, we describe the architecture of RPM, its performance and the prototyping methodology. We also compare our approach with simulation and breadboard prototyping.

Performance Modeling and Characterization of Large Last Level Caches

“…Some of these emulate target system caches like [11], [9] while others emulate the full target system like [2], [4]. MemorIES [11] can emulate several cache configurations with different cache size, line size and associativity.…”

Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution

“…Although, no real information about physical constraints of implementation are provided and till now there is no tested and approved tool assuming conversion of a TLM specification to a synthesizable RTL description. The idea of using FPGA platform for emulating parallel multiprocessors on chip have been used in the RPM [12] and RPM-2 [15] project. Although the approach is based on FPGA neither an automatic exploration flow nor a multi-objective design space exploration approach is proposed.…”

New trends in simulation of distributed shared memory architectures

“…Building the target machine in hardware is an expensive and non-flexible approach. Emulation uses off-the-shelf reconfigurable hardware to emulate different designs [2,20]. Simulation has been the preferable approach since it is flexible and can provide any desired level of detail, but at the cost of a considerable amount of computing resources.…”