“…The tools have been tested on many examples. We plan to use these tools in the testing and verification of industrial embedded programs and extracting communication specific code to synthesise glue logic in System-on-Chip designs [4].…”
In this paper, we present two slicing tools: VHDL Slice and Est slice that compute static executable slices of VHDL and Esterel programs respectively. The slicers have been tested on a number of small and medium sized examples.
“…The tools have been tested on many examples. We plan to use these tools in the testing and verification of industrial embedded programs and extracting communication specific code to synthesise glue logic in System-on-Chip designs [4].…”
In this paper, we present two slicing tools: VHDL Slice and Est slice that compute static executable slices of VHDL and Esterel programs respectively. The slicers have been tested on a number of small and medium sized examples.
“…2 shows a set of results obtained by executing the SER algorithm over some well-known conversion problems described in literature [1]- [3], [8], [19]. Each entry in the table describes the protocols and specification involved and the types converters obtained by using classical approaches and the SER conversion algorithm (D=disabling, DF=disabling and forcing).…”
Section: Implementation Resultsmentioning
confidence: 99%
“…Among the proposed techniques, most approaches use Labeled Transition Systems (LTS) to describe both protocols and specifications, except [5] where CTL temporal logic is used for the specification part. Also, except the approach of [3]- [5] which use oversampling [11] to bridge clock mismatches, all other techniques ignore clock mismatches.…”
Section: Partha Roop Was Supported By Research and Study Leave From Amentioning
confidence: 99%
“…Passerone et al [2] developed a game theoretic formulation to solve the convertibility verification problem. Subsequently, in D'Silva et al [3] a refinement based solution is developed for checking protocol compatibility. Recently, Sinha et al [5] proposed a module checking based solution to the convertibility verification problem.…”
Section: Partha Roop Was Supported By Research and Study Leave From Amentioning
confidence: 99%
“…This is done using the well known idea of disabling from Discrete Event Systems (DES) control theory [12]. Here, a supervisor or controller is synthesized [3] SPA × refinement × disabling Tivoli et al [4] LTS × controlled coverability × implicit disabling Sinha et al [5] LTS CTL model-checking disabling SER Refinement LTS LTS refinement × × disabling, forcing Table 1. Features of various protocol conversion approaches to control a plant so that the controlled system (composition of the controller and the plant) satisfies the desired specification.…”
Section: Partha Roop Was Supported By Research and Study Leave From Amentioning
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.