Proceedings Design, Automation and Test in Europe Conference and Exhibition
DOI: 10.1109/date.2004.1268878
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Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures

Abstract: Plug-n-Play style Intellectual Property(IP) reuse in System on Chip(SoC)

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Cited by 15 publications
(8 citation statements)
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“…The tools have been tested on many examples. We plan to use these tools in the testing and verification of industrial embedded programs and extracting communication specific code to synthesise glue logic in System-on-Chip designs [4].…”
Section: Resultsmentioning
confidence: 99%
“…The tools have been tested on many examples. We plan to use these tools in the testing and verification of industrial embedded programs and extracting communication specific code to synthesise glue logic in System-on-Chip designs [4].…”
Section: Resultsmentioning
confidence: 99%
“…2 shows a set of results obtained by executing the SER algorithm over some well-known conversion problems described in literature [1]- [3], [8], [19]. Each entry in the table describes the protocols and specification involved and the types converters obtained by using classical approaches and the SER conversion algorithm (D=disabling, DF=disabling and forcing).…”
Section: Implementation Resultsmentioning
confidence: 99%
“…Among the proposed techniques, most approaches use Labeled Transition Systems (LTS) to describe both protocols and specifications, except [5] where CTL temporal logic is used for the specification part. Also, except the approach of [3]- [5] which use oversampling [11] to bridge clock mismatches, all other techniques ignore clock mismatches.…”
Section: Partha Roop Was Supported By Research and Study Leave From Amentioning
confidence: 99%
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