Synchronous subnanosecond clock and data recovery for optically switched data centres using clock phase caching

Abstract

The rapid growth of data transferred within data centres, combined with the slowdown in Moore's Law, creates challenges for the future scalability of electronically-switched data-centre networks. Optical switches could offer a future-proof alternative and photonic integration platforms have been recently demonstrated with nanosecond-scale optical switching times. End-to-end switching time, however, is currently limited by the clock and data recovery time, which typically takes microseconds, removing the benefits of nanosecond optical switching. Here we show a clock phase caching technique that can provide clock and data recovery times of under 625 ps (16 symbols at 25.6 Gb/s). Our approach uses the measurement and storage of clock phase values in a synchronised network to simplify clock and data recovery versus conventional asynchronous approaches. We demonstrate our technique using a real-time prototype with commercial transceivers and validate its resilience against temperature variation and clock jitter, based on measurements from a production cloud data centre. Main T he rate of data transmitted between servers within data centres has rapidly increased over the last few years [1], driven by cloud adoption and data-intensive cloud workloads such as data analytics and machine learning. Cloud providers have been able to accommodate this fast growth by relying on Moore's Law for networking: every two years the electronic switch integrated circuits (ICs) double their bandwidth at same cost and power. The long-term sustainability of this trend, however, is being questioned by two upcoming challenges: Firstly, similar to processor ICs, scaling transistor density on electronic switch ICs is fundamentally limited by power dissipation as few-nm transistor sizes are approached [2]. Secondly, electronic high-speed serial transceiver data rates are predicted to be hard to scale beyond 112 Gb/s due to the steep increase in dielectric loss when operating at high frequencies [3, 4]. Consequently, increasing the aggregate switch capacity will require a proportional increase in the number of serial transceivers surrounding the chip, resulting in greater power density and packaging complexity. Although continued bandwidth scaling in the near future could be supported by architectural optimisations such as co-packaged optics [5], preserving cost neutrality in the medium-to-long term appears very challenging. This uncertainty has motivated research in optical switches as a viable alternative to electronic switches [6]. Optical switches simply redirect the incoming signals onto output ports without any optical/electronic conversion or digital processing and, hence, they do not suffer from the limitations of transistor or transceiver technology. They could, therefore, provide a future-proof solution for bandwidth scaling within the data centre [7].

Equalizer State Caching for Fast Data Recovery in Optically-Switched Data Center Networks

“…In this method, the optimal equalizer state (or more specifically, tap coefficients of the equalizer) that corresponds to certain transceiver pairs is stored in respective transceivers and is regularly updated, ensuring that the equalizer state is close to the optimum for the communicating transceivers. This is analogous to the concept of clock phase and amplitude caching that are previously reported in [1,20,21], Equalizer state caching achieves low overhead, low adaptation delay and low DSP complexity for optically switched DCN.…”

“…PTICAL switching is gaining significant interest in data center networks (DCNs) because of its potential to overcome the bandwidth and port density limits in conventional electronic switches [1]. To ensure high network throughput for small packets (e.g., 64 to 576 bytes) dominated DCN [1,2], fast This work was supported in part by in part by EPSRC programme EP/R035342/1, EP/R041792/1 and Royal Society PIF\R1\180001. (Corresponding author: Zhouyi Hu.…”

“…optical switches (e.g., configuration in 1 to 2 nanoseconds) and sub-nanosecond clock and data recovery (CDR) are required [1]. These building blocks are being actively studied, demonstrating sub-nanosecond switching time in an integrated optical switch [3] and sub-nanosecond CDR using clock synchronization and clock phase caching techniques [1].…”

“…Using a receiver-side digital equalizer introduces additional complexity and equalizer adaptation time that did not exist in previously demonstrated on-off-keying (OOK) based systems [1,3,14,15]. For example, standard FFEs/DFEs using least means square (LMS) algorithms require 1000s of symbols to train their tap coefficients, resulting in 100s of nanoseconds data recovery time [1].…”

“…Using a receiver-side digital equalizer introduces additional complexity and equalizer adaptation time that did not exist in previously demonstrated on-off-keying (OOK) based systems [1,3,14,15]. For example, standard FFEs/DFEs using least means square (LMS) algorithms require 1000s of symbols to train their tap coefficients, resulting in 100s of nanoseconds data recovery time [1]. Furthermore, the equalizer state (e.g., tap coefficients in FFEs/DFEs) must be reacquired when switching between different transceiver pairs to compensate for variation of transmission impairments due to, for instance, wavelength drift of the lasers and multiplexers/demultiplexers, as well as different fiber lengths and transceiver bandwidths.…”