SYNTEST: a method for high-level SYNthesis with self-TESTability

Papachristou, C.; Chiu, S.; Harmanani, Haidar M.

doi:10.1109/iccd.1991.139947

Cited by 35 publications

(17 citation statements)

References 14 publications

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“…To deal with the problem of register self-adjacency, methods have been proposed either to avoid producing such self-adjacent registers or to minimize the number of self-adjacent registers during (high-level) synthesis process [1,4,6,8]. Papachristou et al [6] first presented a combined register and ALU allocation method that generates selftestable designs that do not have any self-loops.…”

Section: Introductionmentioning

confidence: 99%

Data path synthesis for BIST with low area overhead

Li¹,

Cheung²

1999

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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Section: Introductionmentioning

confidence: 99%

Data path synthesis for BIST with low area overhead

Li¹,

Cheung²

1999

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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“…Recently, several high level synthesis techniques have been proposed to generate easily testable data paths [Pap91,Lee93,Dey93]. Since presence of loops in a sequential circuit have been shown to be primarily responsible for making sequential automatic test pattern generation difficult, several techniques have been suggested to synthesize data paths without loops, by using proper scheduling and assignment, and scan registers to break loops [Lee93,Dey93].…”

Section: Minimizing Partial Scan Overhead For Improved Testabilitymentioning

confidence: 99%

Optimizing resource utilization and testability using hot potato techniques

Potkonjak

Dey

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is optimized. We demonstrate how the requirements for two important components of the final implementation cost, registers and interconnects, are significantly reduced using new technique. It is also demonstrated how hot potato techniques can be effectively used during high level synthesis to minimize the partial scan overhead to make the synthesized design testable. IntroductionIn this paper, we introduce a new class of transformation techniques, termed hot potato techniques, based on adding deflection operations to the computation structure, while preserving the functionality of the computation.Many operations used in a computation structure has an identity element associated with it. For instance, an addition operation has an identity element zero, while a multiplication operation has an identity element one. If one of the inputs of an operation is v, and the other input is the identity element of the operation, then the output of the operation remains v. Adding such an operation op between two operations op 1 and op 2 has the effect of deflecting the result of op 1 to op, before reaching op 2 ; hence, we term such an operation a deflection operation. A deflection operation can be added anywhere in a computation structure, without changing the functionality of the computation. In addition to demonstrating the effectiveness of the new transformation mechanism for reducing the cost of a design, we also apply the new transformation technique to reduce the partial scan cost needed to make the resultant design testable.We assume that the underlying hardware model is the dedicated register file model. All registers are grouped in a certain number of register files, and each register file can send data to exactly one execution unit. At the same time, each execution unit can send data to an arbitrary number of registers files. This model is used not just in several high level synthesis systems [Rab91], but also in many manual ASIC and general purpose datapaths.In the rest of the paper, we denote an addition by +, a subtraction by -, a multiplication by *, a shift by >>, and input and output by IN and OUT. Also A, S, M and SH denote respectively an adder, subtracter, multiplier and shifter used in the datapath. The left and right inputs to operations and execution units are denoted by L and R respectively. Finally, the positive and negative input of a subtraction and subtracter are labeled by P and S respectively. In all motivational examples, for the sake of simplicity, it is assumed that all operations take one control step for their execution.

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“…A directed edge is drawn from a node i to node j if input of register j can be reached from output of register i through a purely combinational path. A selfloop involving a node i in the structure graph implies poor testability, requiring the register i be configured as a pattern generator and a signature analyzer at the same time, an impossibility unless an area-expensive concurrent BILBO is used [1,7]. The binding phase in the synthesis process is most crucial in minimizing the number of self-loops in the structure graph.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, testability of the generated datapath has assumed importance [1,6,7]. Papachristou et al introduced testable logic blocks ?TLB) in the construction of testable datapaths [7]. A TLB consists of a combinational logic block fed from a register Rl and feeding another register R2.…”

Section: Introductionmentioning

confidence: 99%

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Synthesis of testable pipelined datapaths using genetic search

Ravikumar

Saxena²

Proceedings of 9th International Conference on VLSI Design

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In this paper, we describe TOGAPS, a TestabilityOriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3-D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in the structure graph of the data path. Each design is characterized by a four-tuple consisting of (i) the latency and schedule information, (ii) the module allocation, (iii) operation-to-module binding, and (iv) value-to-register binding. An initial population of designs is constructed from the given data flow graph using different latency cycles whose average latency is in the specified range. Multiple scheduling heuristics are used to generate schedules for the DFG. For each of the resulting scheduled data flow graphs, we decide on an allocation of modules and registers based on a lower bound estimated using the schedule and latency information. The operation-to-module binding and the value-to-register binding are then carried out. A fitness measure is evaluated for each of the resulting data paths; this fitness measure includes one component for each of the three search dimensions. We have implemented TOGAPS on a Sun/SPARC 10 and studied its performance on a number of benchmark examples. Results indicate that TOGAPS finds areaoptimal datapaths for the specified latency cycle, while reducing the number of self-loops in the data path.

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SYNTEST: a method for high-level SYNthesis with self-TESTability

Cited by 35 publications

References 14 publications

Data path synthesis for BIST with low area overhead

Data path synthesis for BIST with low area overhead

Optimizing resource utilization and testability using hot potato techniques

Synthesis of testable pipelined datapaths using genetic search

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