Optimizing resource utilization and testability using hot potato techniques

Abstract

This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is optimized. We demonstrate how the requirements for two important components of the final implementation cost, registers and interconnects, are significantly reduced using new technique. It is also demonstrated how hot potato techniques can be effectively used during high level synthesis to minimize the partial scan overhead to make the synthesized design testable. IntroductionIn this paper, we introduce a new class of transformation techniques, termed hot potato techniques, based on adding deflection operations to the computation structure, while preserving the functionality of the computation.Many operations used in a computation structure has an identity element associated with it. For instance, an addition operation has an identity element zero, while a multiplication operation has an identity element one. If one of the inputs of an operation is v, and the other input is the identity element of the operation, then the output of the operation remains v. Adding such an operation op between two operations op 1 and op 2 has the effect of deflecting the result of op 1 to op, before reaching op 2 ; hence, we term such an operation a deflection operation. A deflection operation can be added anywhere in a computation structure, without changing the functionality of the computation. In addition to demonstrating the effectiveness of the new transformation mechanism for reducing the cost of a design, we also apply the new transformation technique to reduce the partial scan cost needed to make the resultant design testable.We assume that the underlying hardware model is the dedicated register file model. All registers are grouped in a certain number of register files, and each register file can send data to exactly one execution unit. At the same time, each execution unit can send data to an arbitrary number of registers files. This model is used not just in several high level synthesis systems [Rab91], but also in many manual ASIC and general purpose datapaths.In the rest of the paper, we denote an addition by +, a subtraction by -, a multiplication by *, a shift by >>, and input and output by IN and OUT. Also A, S, M and SH denote respectively an adder, subtracter, multiplier and shifter used in the datapath. The left and right inputs to operations and execution units are denoted by L and R respectively. Finally, the positive and negative input of a subtraction and subtracter are labeled by P and S respectively. In all motivational examples, for the sake of simplicity, it is assumed that all operations take one control step for their execution.

Design-for-Debugging of application specific designs

“…The techniques is based on life-time splitting of debugging variables [Kri92,Pot94]. Figure 4 illustrate the considered optimization problem.…”

Improved interconnect sharing by identity operation insertion

“…Heuristics like critical path length or variable lifetimes can be used to exclude edges from the set of possible insertions as has been proposed in [6]. Although this solution offers good results in common cases it does not limit the theoretical complexity of the problem.…”

“…However, none of the approaches mentioned above performs transformations on the CDFG to extend the set of similar patterns. As a first approach to pattern adaptation, [6] presents a CDFG transformation technique, which extends the solution space for the allocation problem. By inserting identity operations (deflection operations) into the CDFG, previously unrelated patterns of operations and data transfers can be aligned, thus increasing the number of similar patterns.…”

“…The result of such a transformation can be seen in figure 1b: The shaded zero-add operation has been inserted, thus eliminating the need for a connection between the multiplier and the shifter. Although based on a local search algoThis work is supported by the Deutsche Forschungsgemeinschaft (DFG) rithm that only considers one identity operation at a time and depends on manual interaction, results in [6] show a large potential for interconnect savings. Still, the criteria for selecting transformations which are most likely to reduce cost in allocation are only roughly sketched.…”